TLV1544 collection procedures, using verilog language, feel useful, hope to adopt

tlv1544\doc\18_SPI接口多通道ADC驱动设计与验证.docx
.......\...\TLV1544.pdf
.......\prj\ip\greybox_tmp\cbx_args.txt
.......\...\..\ISSP.qip
.......\...\..\ISSP.v
.......\...\..\ISSP1.qip
.......\...\..\ISSP1.v
.......\...\..\ISSP1_bb.v
.......\...\..\ISSP_bb.v
.......\...\output_files\Chain3.cdf
.......\...\............\TLV1544_CTRL.asm.rpt
.......\...\............\TLV1544_CTRL.done
.......\...\............\TLV1544_CTRL.eda.rpt
.......\...\............\TLV1544_CTRL.fit.rpt
.......\...\............\TLV1544_CTRL.fit.smsg
.......\...\............\TLV1544_CTRL.fit.summary
.......\...\............\TLV1544_CTRL.flow.rpt
.......\...\............\TLV1544_CTRL.jdi
.......\...\............\TLV1544_CTRL.map.rpt
.......\...\............\TLV1544_CTRL.map.summary
.......\...\............\TLV1544_CTRL.pin
.......\...\............\TLV1544_CTRL.sof
.......\...\............\TLV1544_CTRL.sta.rpt
.......\...\............\TLV1544_CTRL.sta.summary
.......\...\stp1.stp
.......\...\stp1_auto_stripped.stp
.......\...\TLV1544_CTRL.qpf
.......\...\TLV1544_CTRL.qsf
.......\...\TLV1544_CTRL.qws
.......\...\TLV1544_CTRL_nativelink_simulation.rpt
.......\rtl\ADDA_TEST.v
.......\...\ADDA_TEST.v.bak
.......\...\key_filter.v
.......\...\TLC5620_CTRL.v
.......\...\TLV1544_CTRL.v
.......\...\TLV1544_CTRL.v.bak
.......\sim\TLV1544_CTRL_tb.cr.mti
.......\...\TLV1544_CTRL_tb.mpf
.......\...\vsim.wlf
.......\...\work\@a@d@d@a_@t@e@s@t\_primary.dat
.......\...\....\.................\_primary.dbs
.......\...\....\.................\_primary.vhd
.......\...\....\.t@l@c5620_@c@t@r@l\_primary.dat
.......\...\....\...................\_primary.dbs
.......\...\....\...................\_primary.vhd
.......\...\....\.....v1544_@c@t@r@l\verilog.asm64
.......\...\....\...................\verilog.rw64
.......\...\....\...................\_primary.dat
.......\...\....\...................\_primary.dbs
.......\...\....\...................\_primary.vhd
.......\...\....\..................._tb\verilog.asm64
.......\...\....\......................\verilog.rw64
.......\...\....\......................\_primary.dat
.......\...\....\......................\_primary.dbs
.......\...\....\......................\_primary.vhd
.......\...\....\key_filter\_primary.dat
.......\...\....\..........\_primary.dbs
.......\...\....\..........\_primary.vhd
.......\...\....\_info
.......\...\....\.temp\vlog2ex9z1
.......\...\....\.....\vlog543fjz
.......\...\....\_vmake
.......\testbench\TLV1544_CTRL_tb.v
.......\prj\ip\greybox_tmp
.......\sim\work\@a@d@d@a_@t@e@s@t
.......\...\....\@t@l@c5620_@c@t@r@l
.......\...\....\@t@l@v1544_@c@t@r@l
.......\...\....\@t@l@v1544_@c@t@r@l_tb
.......\...\....\key_filter
.......\...\....\_temp
.......\prj\ip
.......\...\output_files
.......\sim\work
.......\doc
.......\img
.......\par
.......\prj
.......\rtl
.......\sim
.......\src
.......\tb
.......\testbench
tlv1544

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