Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.

DDS(ok)
.......\db
.......\..\altsyncram_kf91.tdf
.......\..\altsyncram_mf91.tdf
.......\..\DDS.asm.qmsg
.......\..\DDS.asm.rdb
.......\..\DDS.asm_labs.ddb
.......\..\DDS.cbx.xml
.......\..\DDS.cmp.bpm
.......\..\DDS.cmp.cdb
.......\..\DDS.cmp.hdb
.......\..\DDS.cmp.idb
.......\..\DDS.cmp.kpt
.......\..\DDS.cmp.logdb
.......\..\DDS.cmp.rdb
.......\..\DDS.cmp_merge.kpt
.......\..\DDS.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.......\..\DDS.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
.......\..\DDS.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.......\..\DDS.db_info
.......\..\DDS.eda.qmsg
.......\..\DDS.fit.qmsg
.......\..\DDS.hier_info
.......\..\DDS.hif
.......\..\DDS.ipinfo
.......\..\DDS.lpc.html
.......\..\DDS.lpc.rdb
.......\..\DDS.lpc.txt
.......\..\DDS.map.ammdb
.......\..\DDS.map.bpm
.......\..\DDS.map.cdb
.......\..\DDS.map.hdb
.......\..\DDS.map.kpt
.......\..\DDS.map.logdb
.......\..\DDS.map.qmsg
.......\..\DDS.map.rdb
.......\..\DDS.map_bb.cdb
.......\..\DDS.map_bb.hdb
.......\..\DDS.map_bb.logdb
.......\..\DDS.pre_map.hdb
.......\..\DDS.pti_db_list.ddb
.......\..\DDS.root_partition.map.reg_db.cdb
.......\..\DDS.routing.rdb
.......\..\DDS.rtlv.hdb
.......\..\DDS.rtlv_sg.cdb
.......\..\DDS.rtlv_sg_swap.cdb
.......\..\DDS.sgdiff.cdb
.......\..\DDS.sgdiff.hdb
.......\..\DDS.sld_design_entry.sci
.......\..\DDS.sld_design_entry_dsc.sci
.......\..\DDS.smart_action.txt
.......\..\DDS.sta.qmsg
.......\..\DDS.sta.rdb
.......\..\DDS.sta_cmp.8_slow_1200mv_85c.tdb
.......\..\DDS.syn_hier_info
.......\..\DDS.tiscmp.fastest_slow_1200mv_0c.ddb
.......\..\DDS.tiscmp.fastest_slow_1200mv_85c.ddb
.......\..\DDS.tiscmp.fast_1200mv_0c.ddb
.......\..\DDS.tiscmp.slow_1200mv_0c.ddb
.......\..\DDS.tiscmp.slow_1200mv_85c.ddb
.......\..\DDS.tis_db_list.ddb
.......\..\DDS.tmw_info
.......\..\DDS.vpr.ammdb
.......\..\logic_util_heursitic.dat
.......\..\PLL_altpll.v
.......\..\prev_cmp_DDS.qmsg
.......\DDS.asm.rpt
.......\DDS.done
.......\DDS.eda.rpt
.......\DDS.fit.rpt
.......\DDS.fit.smsg
.......\DDS.fit.summary
.......\DDS.flow.rpt
.......\DDS.jdi
.......\DDS.map.rpt
.......\DDS.map.summary
.......\DDS.pin
.......\DDS.qpf
.......\DDS.qsf
.......\DDS.qws
.......\DDS.sof
.......\DDS.sta.rpt
.......\DDS.sta.summary
.......\DDS.v
.......\DDS.v.bak
.......\DDS_assignment_defaults.qdf
.......\DDS_nativelink_simulation.rpt
.......\DDS_ROM.mif
.......\DDS_tb.v
.......\greybox_tmp
.......\...........\cbx_args.txt
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\DDS.db_info
.......\..............\...................\DDS.root_partition.cmp.ammdb
.......\..............\...................\DDS.root_partition.cmp.cdb
.......\..............\...................\DDS.root_partition.cmp.dfp
.......\..............\...................\DDS.root_partition.cmp.hdb
.......\..............\...................\DDS.root_partition.cmp.kpt
.......\..............\...................\DDS.root_partition.cmp.logdb

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