this a sample of sequential circuit in verilog and VHDL

Rangkaian Sekuensial VHDL & Verilog\Verilog\Counter\counter.cr.mti
...................................\.......\.......\counter.do
...................................\.......\.......\counter.mpf
...................................\.......\.......\counter.v
...................................\.......\.......\counter.v.bak
...................................\.......\.......\vsim.wlf
...................................\.......\.......\work\counter\verilog.prw
...................................\.......\.......\....\.......\verilog.psm
...................................\.......\.......\....\.......\_primary.dat
...................................\.......\.......\....\.......\_primary.dbs
...................................\.......\.......\....\.......\_primary.vhd
...................................\.......\.......\....\_info
...................................\.......\.......\....\_vmake
...................................\.......\D flip flop\dff
...................................\.......\...........\dff.cr.mti
...................................\.......\...........\dff.do
...................................\.......\...........\dff.do.bak
...................................\.......\...........\dff.mpf
...................................\.......\...........\dff.v
...................................\.......\...........\dff.v.bak
...................................\.......\...........\vsim.wlf
...................................\.......\...........\wave.do
...................................\.......\...........\.ork\dff\verilog.prw
...................................\.......\...........\....\...\verilog.psm
...................................\.......\...........\....\...\_primary.dat
...................................\.......\...........\....\...\_primary.dbs
...................................\.......\...........\....\...\_primary.vhd
...................................\.......\...........\....\_info
...................................\.......\...........\....\_vmake
...................................\.......\Paralel To Serial\paraleltoserial
...................................\.......\.................\paraleltoserial.cr.mti
...................................\.......\.................\paraleltoserial.do
...................................\.......\.................\paraleltoserial.do.bak
...................................\.......\.................\paraleltoserial.mpf
...................................\.......\.................\paraleltoserial.v
...................................\.......\.................\paraleltoserial.v.bak
...................................\.......\.................\vsim.wlf
...................................\.......\.................\work\prl2srl\verilog.prw
...................................\.......\.................\....\.......\verilog.psm
...................................\.......\.................\....\.......\_primary.dat
...................................\.......\.................\....\.......\_primary.dbs
...................................\.......\.................\....\.......\_primary.vhd
...................................\.......\.................\....\_info
...................................\.......\.................\....\_vmake
...................................\.......\Trafic Light\dff.cr.mti
...................................\.......\............\dff.mpf
...................................\.......\............\traffic.cr.mti
...................................\.......\............\traffic.do
...................................\.......\............\traffic.mpf
...................................\.......\............\traffic.v
...................................\.......\............\traffic.v.bak
...................................\.......\............\vsim.wlf
...................................\.......\............\work\traffic\verilog.prw
...................................\.......\............\....\.......\verilog.psm
...................................\.......\............\....\.......\_primary.dat
...................................\.......\............\....\.......

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