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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-10-12
  • Size : 24kb
  • Downloaded :0次
  • Author :moh****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
its a Universal ART code writen by VHDL
Packet file list
(Preview for download)


ipcore_dir
iseconfig
.........\main_ser_to_par.xreport
main_ser_to_par.jhd
main_ser_to_par.sch
main_ser_to_par.schlog
main_ser_to_par_summary.html
pepExtractor.prj
UART6.gise
UART6.xise
uart_rx6.cmd_log
uart_rx6.spl
uart_rx6.sym
uart_rx6.vhd
uart_tx6.cmd_log
uart_tx6.spl
uart_tx6.sym
uart_tx6.vhd
_xmsgs
......\pn_parser.xmsgs
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