Use quartus platform verilog language Direct Digital Synthesis

xuexidds
........\acc.bsf
........\acc.v
........\acc_bb.v
........\adder.bsf
........\adder.v
........\address_decode.bsf
........\address_decode.v
........\addrlatch.bdf
........\atof.bsf
........\atof.v
........\control.bsf
........\control.v
........\count.bsf
........\count.v
........\count_bb.v
........\db
........\..\dds.db_info
........\..\dds.sld_design_entry.sci
........\..\prev_cmp_dds.qmsg
........\dds.bdf
........\dds.done
........\dds.qpf
........\dds.qsf
........\dds.v
........\e1.bdf
........\lshift.bsf
........\lshift.v
........\lshift_bb.v
........\m.bdf
........\multam.bsf
........\multam.v
........\multam_bb.v
........\ram.bsf
........\ram.v
........\ram_bb.v

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