Realize five-stage pipeline CPU

pcpu_handle_mem\clk_div.v
...............\clk_div_isim_beh.exe
...............\cpu.bgn
...............\cpu.bit
...............\cpu.bld
...............\cpu.cmd_log
...............\cpu.drc
...............\cpu.lso
...............\cpu.ncd
...............\cpu.ngc
...............\cpu.ngd
...............\cpu.ngr
...............\cpu.pad
...............\cpu.par
...............\cpu.pcf
...............\cpu.prj
...............\cpu.ptwx
...............\cpu.stx
...............\cpu.syr
...............\cpu.twr
...............\cpu.twx
...............\cpu.unroutes
...............\cpu.ut
...............\cpu.v
...............\cpu.xpi
...............\cpu.xst
...............\cpu_bitgen.xwbt
...............\cpu_envsettings.html
...............\cpu_guide.ncd
...............\cpu_icf.ucf
...............\cpu_isim_beh.exe
...............\cpu_map.map
...............\cpu_map.mrp
...............\cpu_map.ncd
...............\cpu_map.ngm
...............\cpu_map.xrpt
...............\cpu_ngdbuild.xrpt
...............\cpu_pad.csv
...............\cpu_pad.txt
...............\cpu_par.xrpt
...............\cpu_summary.html
...............\cpu_summary.xml
...............\cpu_tb.v
...............\cpu_tb2.v
...............\cpu_tb2_beh.prj
...............\cpu_tb2_isim_beh.exe
...............\cpu_tb2_isim_beh.wdb
...............\cpu_tb_beh.prj
...............\cpu_tb_isim_beh.exe
...............\cpu_tb_isim_beh.wdb
...............\cpu_tb_stx_beh.prj
...............\cpu_usage.xml
...............\cpu_xst.xrpt
...............\data_cache.v
...............\data_cache_isim_beh.exe
...............\data_mem.v
...............\data_mem_isim_beh.exe
...............\d_mem.mif
...............\d_mem.v
...............\fuse.log
...............\fuse.xmsgs
...............\fuseRelaunch.cmd
...............\inst_mem.v
...............\inst_mem_isim_beh.exe
...............\inst_mem_isim_beh1.wdb
...............\.pcore_dir\coregen.cgp
...............\..........\coregen.log
...............\..........\create_d_mem.tcl
...............\..........\create_i_mem.tcl
...............\..........\d_mem\blk_mem_gen_v7_3_readme.txt
...............\..........\.....\doc\blk_mem_gen_v7_3_vinfo.html
...............\..........\.....\...\pg058-blk-mem-gen.pdf
...............\..........\.....\example_design\d_mem_exdes.ucf
...............\..........\.....\..............\d_mem_exdes.vhd
...............\..........\.....\..............\d_mem_exdes.xdc
...............\..........\.....\..............\d_mem_prod.vhd
...............\..........\.....\implement\implement.bat
...............\..........\.....\.........\implement.sh
...............\..........\.....\.........\planAhead_ise.bat
...............\..........\.....\.........\planAhead_ise.sh
...............\..........\.....\.........\planAhead_ise.tcl
...............\..........\.....\.........\xst.prj
...............\..........\.....\.........\xst.scr
...............\..........\.....\simulation\addr_gen.vhd
...............\..........\.....\..........\bmg_stim_gen.vhd
...............\..........\.....\..........\bmg_tb_pkg.vhd
...............\..........\.....\..........\checker.vhd
...............\..........\.....\..........\data_gen.vhd
...............\..........\.....\..........\d_mem_synth.vhd
...............\..........\.....\..........\d_mem_tb.vhd
...............\..........\.....\..........\functional\simcmds.tcl
...............\..........\.....\..........\..........\simulate_isim.bat
...............\..........\.....\..........\..........\simulate_mti.bat
...............\..........\.....\..........\..........\simulate_mti.do
...............\..........\.....\..........\..........\simulate_mti.sh
...............\..........\.....\..........\..........\simulate_ncsim.sh
...............\..........\.....\..........\..........\simulate_vcs.sh
...............\..........\.....\..........\..........\ucli_commands.key
...............\..........\.....\..........\..........\vcs_session.tcl
...............\..........\.....\..........\..........\wave_mti.do

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