Multi-cycle CPU design of the controller.

OExp11-OwnMCPU
..............\clk_div.sym
..............\code
..............\....\clk_div.v
..............\....\Counter_3_IO.v
..............\....\ctrl.v
..............\....\Ext_32.v
..............\....\MIO_BUS_IO.v
..............\....\Multi_8CH32_IO.v
..............\....\MUX2T1_32.v
..............\....\MUX4T1_32.v
..............\....\MUX4T1_5.v
..............\....\M_datapath.v
..............\....\OExp_ALU.v
..............\....\PIO_IO.v
..............\....\REG32.v
..............\....\Regs.v
..............\....\SAnti_jitter_IO.v
..............\....\Seg7_Dev_IO.v
..............\....\SEnter_2_32_IO.v
..............\....\SPIO_IO.v
..............\....\SSeg7_Dev_IO.v
..............\Counter_x.ngc
..............\Counter_x.sym
..............\ctrl.ngc
..............\ctrl.sym
..............\Ext_32.sym
..............\ipcore_dir
..............\..........\coregen.cgp
..............\..........\coregen.log
..............\..........\create_RAM_B.tcl
..............\..........\RAM_B
..............\..........\RAM_B.asy
..............\..........\RAM_B.gise
..............\..........\RAM_B.mif
..............\..........\RAM_B.ncf
..............\..........\RAM_B.ngc
..............\..........\RAM_B.sym
..............\..........\RAM_B.v
..............\..........\RAM_B.veo
..............\..........\RAM_B.xco
..............\..........\RAM_B.xise
..............\..........\.....\blk_mem_gen_v7_3_readme.txt
..............\..........\.....\doc
..............\..........\.....\...\blk_mem_gen_v7_3_vinfo.html
..............\..........\.....\...\pg058-blk-mem-gen.pdf
..............\..........\.....\example_design
..............\..........\.....\..............\RAM_B_exdes.ucf
..............\..........\.....\..............\RAM_B_exdes.vhd
..............\..........\.....\..............\RAM_B_exdes.xdc
..............\..........\.....\..............\RAM_B_prod.vhd
..............\..........\.....\implement
..............\..........\.....\.........\implement.bat
..............\..........\.....\.........\implement.sh
..............\..........\.....\.........\planAhead_ise.bat
..............\..........\.....\.........\planAhead_ise.sh
..............\..........\.....\.........\planAhead_ise.tcl
..............\..........\.....\.........\xst.prj
..............\..........\.....\.........\xst.scr
..............\..........\.....\simulation
..............\..........\.....\..........\addr_gen.vhd
..............\..........\.....\..........\bmg_stim_gen.vhd
..............\..........\.....\..........\bmg_tb_pkg.vhd
..............\..........\.....\..........\checker.vhd
..............\..........\.....\..........\data_gen.vhd
..............\..........\.....\..........\functional
..............\..........\.....\..........\..........\simcmds.tcl
..............\..........\.....\..........\..........\simulate_isim.bat
..............\..........\.....\..........\..........\simulate_mti.bat
..............\..........\.....\..........\..........\simulate_mti.do
..............\..........\.....\..........\..........\simulate_mti.sh
..............\..........\.....\..........\..........\simulate_ncsim.sh
..............\..........\.....\..........\..........\simulate_vcs.sh
..............\..........\.....\..........\..........\ucli_commands.key
..............\..........\.....\..........\..........\vcs_session.tcl
..............\..........\.....\..........\..........\wave_mti.do
..............\..........\.....\..........\..........\wave_ncsim.sv
..............\..........\.....\..........\RAM_B_synth.vhd
..............\..........\.....\..........\RAM_B_tb.vhd
..............\..........\.....\..........\random.vhd
..............\..........\.....\..........\timing
..............\..........\.....\..........\......\simcmds.tcl
..............\..........\.....\..........\......\simulate_isim.bat
..............\..........\.....\..........\......\simulate_mti.bat
..............\..........\.....\..........\......\simulate_mti.do
..............\..........\.....\..........\......\simulate_mti.sh
..............\..........\.....\..........\......\simulate_ncsim.sh
..............\..........\.....\........

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