DVI encode and decode in Verlog language.Have been tested in altera FPGA Cycloene IV

dvi_demo\rtl\common\debnce.v
........\...\......\DRAM16XN.v
........\...\......\hdclrbar.v
........\...\......\synchro.v
........\...\......\timing.v
........\...\dvitx_demo.v
........\...\dvi_demo.v
........\...\logofly\autopilot.v
........\...\.......\cursor_pair.v
........\...\.......\s3a_logo.v
........\...\rx\chnlbond.v
........\...\..\dcminit.v
........\...\..\decode.v
........\...\..\dvi_decoder.v
........\...\..\phsaligner.v
........\...\..\tmds_1c_1to10.v
........\...\tx\dvi_encoder.v
........\...\..\encode.v
........\...\..\serdes_4b_10to1_fifo.v
........\...\common
........\...\logofly
........\...\rx
........\...\tx
........\rtl
dvi_demo

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