Mainly use Verilog code programming serial port to receive

class11_uart_rx
...............\doc
...............\img
...............\modelsim_uart_rx
...............\................\modelsim.ini
...............\................\uart_byte_rx
...............\................\............\@_opt
...............\................\............\.....\_deps
...............\................\............\.....\vopt23fhy7
...............\................\............\.....\vopt5sgwhx
...............\................\............\.....\vopt8fi75j
...............\................\............\.....\voptb5kir8
...............\................\............\.....\voptevmxby
...............\................\............\.....\vopthhq8zj
...............\................\............\.....\voptjk6txv
...............\................\............\.....\voptk7sji9
...............\................\............\.....\voptna85hh
...............\................\............\.....\voptqxty5z
...............\................\............\.....\vopts0ag47
...............\................\............\.....\vopttjw9sk
...............\................\............\.....\voptwnbvqw
...............\................\............\.....\voptx9ykca
...............\................\............\.....\voptzcd6bi
...............\................\............\_info
...............\................\............\_temp
...............\................\............\.....\vlogg6s7z0
...............\................\............\_vmake
...............\................\............\uart_byte_rx
...............\................\............\............\_primary.dat
...............\................\............\............\_primary.dbs
...............\................\............\............\_primary.vhd
...............\................\............\............\verilog.asm
...............\................\............\............\verilog.rw
...............\................\............\uart_byte_rx_tb
...............\................\............\...............\_primary.dat
...............\................\............\...............\_primary.dbs
...............\................\............\...............\_primary.vhd
...............\................\............\...............\verilog.asm
...............\................\............\...............\verilog.rw
...............\................\............\uart_byte_tx
...............\................\............\............\_primary.dat
...............\................\............\............\_primary.dbs
...............\................\............\............\_primary.vhd
...............\................\............\............\verilog.asm
...............\................\............\............\verilog.rw
...............\................\uart_byte_rx.v
...............\................\uart_byte_rx.v.bak
...............\................\uart_byte_rx_tb.cr.mti
...............\................\uart_byte_rx_tb.mpf
...............\................\uart_byte_rx_tb.v
...............\................\vsim.wlf
...............\................\wave.do
...............\prj
...............\...\Spf1.spf
...............\...\db
...............\...\..\logic_util_heursitic.dat
...............\...\..\prev_cmp_uart_byte_rx.qmsg
...............\...\..\uart_byte_rx.amm.cdb
...............\...\..\uart_byte_rx.asm.qmsg
...............\...\..\uart_byte_rx.asm.rdb
...............\...\..\uart_byte_rx.asm_labs.ddb
...............\...\..\uart_byte_rx.autoh_e4eb1.map.reg_db.cdb
...............\...\..\uart_byte_rx.cbx.xml
...............\...\..\uart_byte_rx.cmp.bpm
...............\...\..\uart_byte_rx.cmp.cdb
...............\...\..\uart_byte_rx.cmp.hdb
...............\...\..\uart_byte_rx.cmp.kpt
...............\...\..\uart_byte_rx.cmp.logdb
...............\...\..\uart_byte_rx.cmp.rdb
...............\...\..\uart_byte_rx.cmp_merge.kpt
...............\...\..\uart_byte_rx.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
...............\...\..\uart_byte_rx.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
...............\...\..\uart_byte_rx.cycloneive_io_sim_cache.45um_ss_1200mv_85c

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