The source for the FPGA-based HDMI display of a four of the AV video capture. The module can be easily transplanted in the need to use the HDMI high-definition display occasions, and VGA display can be divided into four, to facilitate the display of different windows of different image information

vip_ex17\.qsys_edit\filters.xml
........\..........\layout.xml
........\..........\preferences.xml
........\..........\vip_qsys.xml
........\altmemphy-library\auk_ddr_hp_controller.ocp
........\alt_mem_ddrx_addr_cmd.v
........\alt_mem_ddrx_addr_cmd_wrap.v
........\alt_mem_ddrx_arbiter.v
........\alt_mem_ddrx_buffer.v
........\alt_mem_ddrx_buffer_manager.v
........\alt_mem_ddrx_burst_gen.v
........\alt_mem_ddrx_burst_tracking.v
........\alt_mem_ddrx_cmd_gen.v
........\alt_mem_ddrx_controller.v
........\alt_mem_ddrx_controller_st_top.v
........\alt_mem_ddrx_csr.v
........\alt_mem_ddrx_dataid_manager.v
........\alt_mem_ddrx_ddr2_odt_gen.v
........\alt_mem_ddrx_ddr3_odt_gen.v
........\alt_mem_ddrx_define.iv
........\alt_mem_ddrx_ecc_decoder.v
........\alt_mem_ddrx_ecc_decoder_32_syn.v
........\alt_mem_ddrx_ecc_decoder_64_syn.v
........\alt_mem_ddrx_ecc_encoder.v
........\alt_mem_ddrx_ecc_encoder_32_syn.v
........\alt_mem_ddrx_ecc_encoder_64_syn.v
........\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
........\alt_mem_ddrx_fifo.v
........\alt_mem_ddrx_input_if.v
........\alt_mem_ddrx_list.v
........\alt_mem_ddrx_lpddr2_addr_cmd.v
........\alt_mem_ddrx_mm_st_converter.v
........\alt_mem_ddrx_odt_gen.v
........\alt_mem_ddrx_rank_timer.v
........\alt_mem_ddrx_rdata_path.v
........\alt_mem_ddrx_rdwr_data_tmg.v
........\alt_mem_ddrx_sideband.v
........\alt_mem_ddrx_tbp.v
........\alt_mem_ddrx_timing_param.v
........\alt_mem_ddrx_wdata_path.v
........\alt_mem_phy_defines.v
........\data_source.v
........\.b\vip.db_info
........\..\vip.ipinfo
........\..\vip.sld_design_entry.sci
........\dbsr_ctrl.qip
........\dbsr_ctrl.v
........\dbsr_ctrl_bb.v
........\dbsr_ctrl_inst.v
........\ddr2_controller.bsf
........\ddr2_controller.cmp
........\ddr2_controller.html
........\ddr2_controller.ppf
........\ddr2_controller.qip
........\ddr2_controller.v
........\ddr2_controller_advisor.ipa
........\ddr2_controller_alt_mem_ddrx_controller_top.v
........\ddr2_controller_bb.v
........\ddr2_controller_controller_phy.v
........\ddr2_controller_example_driver.v
........\ddr2_controller_example_top.sdc
........\ddr2_controller_example_top.v
........\ddr2_controller_example_top.v.tmp2
........\ddr2_controller_example_top_1.v
........\ddr2_controller_example_top_2.v
........\ddr2_controller_ex_lfsr8.v
........\ddr2_controller_phy.bsf
........\ddr2_controller_phy.cmp
........\ddr2_controller_phy.html
........\ddr2_controller_phy.qip
........\ddr2_controller_phy.v
........\ddr2_controller_phy_alt_mem_phy.v
........\ddr2_controller_phy_alt_mem_phy_pll.qip
........\ddr2_controller_phy_alt_mem_phy_pll.v
........\ddr2_controller_phy_alt_mem_phy_pll.v_.bak
........\ddr2_controller_phy_alt_mem_phy_pll_bb.v
........\ddr2_controller_phy_alt_mem_phy_seq.vhd
........\ddr2_controller_phy_alt_mem_phy_seq_wrapper.v
........\ddr2_controller_phy_autodetectedpins.tcl
........\ddr2_controller_phy_bb.v
........\ddr2_controller_phy_ddr_pins.tcl
........\ddr2_controller_phy_ddr_timing.sdc
........\ddr2_controller_phy_ddr_timing.tcl
........\ddr2_controller_phy_report_timing.tcl
........\ddr2_controller_phy_report_timing_core.tcl
........\ddr2_controller_phy_summary.csv
........\ddr2_controller_pin_assignments.tcl
........\.....high_performance_controller-library\auk_ddr_hp_controller.ocp
........\greybox_tmp\cbx_args.txt
........\IIC_CONTROLLER_hw.tcl
........\IIC_CONTROLLER_hw.tcl~
........\kfifo_ctrl.qip
........\kfifo_ctrl.v
........\kfifo_ctrl_bb.v
........\kfifo_ctrl_inst.v
........\led_controller.v
........\muxadd.qip
........\muxadd.v
........\muxadd2.qip
........\muxadd2.v

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