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dma_bridge_verilog

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-11-30
  • Size : 33kb
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  • Author :bo***
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Introduction - If you have any usage issues, please Google them yourself
DMA control module design reference, for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
Packet file list
(Preview for download)


8dma_bridge\wb_dma8\wb_bridge_and_dma.v
...........\.......\wb_dma_ch_arb8.v
...........\.......\wb_dma_ch_pri_enc8.v
...........\.......\wb_dma_ch_rf8.v
...........\.......\wb_dma_ch_sel8.v
...........\.......\wb_dma_de8.v
...........\.......\wb_dma_defines.v
...........\.......\wb_dma_inc30r8.v
...........\.......\wb_dma_pri_enc_sub8.v
...........\.......\wb_dma_registers.v
...........\.......\wb_dma_rf8.v
...........\.......\wb_dma_top8.v
...........\.......\wb_dma_wb_if8.v
...........\.......\wb_dma_wb_mast8.v
...........\.......\wb_dma_wb_slv8.v
...........\.......\wb_flash.v
...........\.......\wb_intf2.v
...........\.......\wb_seg4x7.v
...........\.......\wb_slave.v
...........\.......\wb_tab.v
...........\wb_dma8
8dma_bridge
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