ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface

adi_common_v1_00_a\hdl\verilog\cf_gtx_es_if.v
..................\...\.......\cf_gtx_es_wr.v
..................\...\.......\cf_jesd_align_2.v
..................\...\.......\cf_jesd_mon.v
..................\...\.......\cf_mem.v
.xi_ad9250_v1_00_a\data\axi_ad9250_v2_1_0.mpd
..................\....\axi_ad9250_v2_1_0.pao
..................\....\_axi_ad9250_xst.prj
..................\hdl\verilog\cf_ad9250.v
..................\...\.......\cf_adc_if.v
..................\...\.......\cf_dma_wr.v
..................\...\.......\cf_mem.v
..................\...\.......\cf_pnmon.v
..................\...\.......\user_logic.v
..................\...\.hdl\axi_ad9250.vhd
..................\regmap.txt
....clkgen_v1_00_a\data\axi_clkgen_v2_1_0.mpd
..................\....\axi_clkgen_v2_1_0.pao
..................\....\_axi_clkgen_xst.prj
..................\hdl\verilog\cf_clkgen.v
..................\...\.......\user_logic.v
..................\...\.hdl\axi_clkgen.vhd
..................\regmap.txt
....jesd204b_rx2_v1_00_a\cf_jesd_core.cdc
........................\data\axi_jesd204b_rx2_v2_1_0.bbd
........................\....\axi_jesd204b_rx2_v2_1_0.mpd
........................\....\axi_jesd204b_rx2_v2_1_0.pao
........................\....\_axi_jesd204b_rx2_xst.prj
........................\hdl\verilog\jesd204b_rx2_gtwizard_v2_1.v
........................\...\.......\jesd204b_rx2_gtwizard_v2_1_gt.v
........................\...\.......\jesd204b_rx2_gtwizard_v2_1_top.v
........................\...\.......\jesd204b_rx2_top.v
........................\...\.......\user_logic.v
........................\...\.hdl\axi_jesd204b_rx2.vhd
........................\netlist\jesd204b_rx2.xco
........................\regmap.txt
util_jesdbuf_v1_00_a\data\util_jesdbuf_v2_1_0.mpd
....................\....\util_jesdbuf_v2_1_0.pao
....................\hdl\vhdl\util_jesdbuf.vhd
adi_common_v1_00_a\hdl\verilog
.xi_ad9250_v1_00_a\hdl\verilog
..................\...\vhdl
....clkgen_v1_00_a\hdl\verilog
..................\...\vhdl
....jesd204b_rx2_v1_00_a\hdl\verilog
........................\...\vhdl
util_jesdbuf_v1_00_a\hdl\vhdl
adi_common_v1_00_a\hdl
.xi_ad9250_v1_00_a\data
..................\hdl
....clkgen_v1_00_a\data
..................\hdl
....jesd204b_rx2_v1_00_a\data
........................\hdl
........................\netlist
util_jesdbuf_v1_00_a\data
....................\hdl
adi_common_v1_00_a
axi_ad9250_v1_00_a
axi_clkgen_v1_00_a
axi_jesd204b_rx2_v1_00_a
util_jesdbuf_v1_00_a

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