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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-12-11
  • Size : 333kb
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  • Author :杜****
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Introduction - If you have any usage issues, please Google them yourself
FPGA simple program, enabling a digital display, the display cycles 0-9
Packet file list
(Preview for download)


seg
...\db
...\..\logic_util_heursitic.dat
...\..\prev_cmp_seg.qmsg
...\..\seg.asm.qmsg
...\..\seg.asm.rdb
...\..\seg.cbx.xml
...\..\seg.cmp.idb
...\..\seg.cmp.kpt
...\..\seg.cmp.rdb
...\..\seg.cmp0.ddb
...\..\seg.cmp1.ddb
...\..\seg.cmp_merge.kpt
...\..\seg.db_info
...\..\seg.eda.qmsg
...\..\seg.fit.qmsg
...\..\seg.hier_info
...\..\seg.hif
...\..\seg.ipinfo
...\..\seg.lpc.html
...\..\seg.lpc.rdb
...\..\seg.lpc.txt
...\..\seg.map.ammdb
...\..\seg.map.bpm
...\..\seg.map.cdb
...\..\seg.map.hdb
...\..\seg.map.kpt
...\..\seg.map.logdb
...\..\seg.map.qmsg
...\..\seg.map.rdb
...\..\seg.map_bb.cdb
...\..\seg.map_bb.hdb
...\..\seg.map_bb.logdb
...\..\seg.pplq.rdb
...\..\seg.pre_map.hdb
...\..\seg.pti_db_list.ddb
...\..\seg.root_partition.map.reg_db.cdb
...\..\seg.routing.rdb
...\..\seg.rtlv.hdb
...\..\seg.rtlv_sg.cdb
...\..\seg.rtlv_sg_swap.cdb
...\..\seg.sgdiff.cdb
...\..\seg.sgdiff.hdb
...\..\seg.sld_design_entry.sci
...\..\seg.sld_design_entry_dsc.sci
...\..\seg.smart_action.txt
...\..\seg.sta.qmsg
...\..\seg.sta.rdb
...\..\seg.syn_hier_info
...\..\seg.tis_db_list.ddb
...\..\seg.tmw_info
...\..\seg.vpr.ammdb
...\incremental_db
...\..............\README
...\..............\compiled_partitions
...\..............\...................\seg.db_info
...\..............\...................\seg.root_partition.cmp.ammdb
...\..............\...................\seg.root_partition.cmp.cdb
...\..............\...................\seg.root_partition.cmp.dfp
...\..............\...................\seg.root_partition.cmp.hdb
...\..............\...................\seg.root_partition.cmp.kpt
...\..............\...................\seg.root_partition.cmp.logdb
...\..............\...................\seg.root_partition.cmp.rcfdb
...\..............\...................\seg.root_partition.map.cdb
...\..............\...................\seg.root_partition.map.dpi
...\..............\...................\seg.root_partition.map.hbdb.cdb
...\..............\...................\seg.root_partition.map.hbdb.hb_info
...\..............\...................\seg.root_partition.map.hbdb.hdb
...\..............\...................\seg.root_partition.map.hbdb.sig
...\..............\...................\seg.root_partition.map.hdb
...\..............\...................\seg.root_partition.map.kpt
...\output_files
...\............\Chain3.cdf
...\............\output_files
...\............\seg.asm.rpt
...\............\seg.done
...\............\seg.eda.rpt
...\............\seg.fit.rpt
...\............\seg.fit.smsg
...\............\seg.fit.summary
...\............\seg.flow.rpt
...\............\seg.jdi
...\............\seg.map.rpt
...\............\seg.map.smsg
...\............\seg.map.summary
...\............\seg.pin
...\............\seg.pof
...\............\seg.sof
...\............\seg.sta.rpt
...\............\seg.sta.summary
...\seg.qpf
...\seg.qsf
...\seg.qws
...\seg.v
...\seg.v.bak
...\seg_nativelink_simulation.rpt
...\segtestbench.v
...\segtestbench.v.bak
...\simulation
...\..........\modelsim
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