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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-12-12
  • Size : 80kb
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  • Author :med***
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Introduction to learn laboratry with altera quartus II 9.1
Packet file list
(Preview for download)


Lab_5\7segment.bsf
.....\7segment.tdf
.....\cmp_state.ini
.....\db
.....\LiveDesign.asm.rpt
.....\LiveDesign.cdf
.....\LiveDesign.done
.....\LiveDesign.fit.eqn
.....\LiveDesign.fit.rpt
.....\LiveDesign.fit.summary
.....\LiveDesign.flow.rpt
.....\LiveDesign.map.eqn
.....\LiveDesign.map.rpt
.....\LiveDesign.map.summary
.....\LiveDesign.pin
.....\LiveDesign.pof
.....\LiveDesign.qpf
.....\LiveDesign.qsf
.....\LiveDesign.qws
.....\LiveDesign.sim.rpt
.....\LiveDesign.sof
.....\LiveDesign.tan.rpt
.....\LiveDesign.tan.summary
.....\LiveDesign_description.txt
.....\TopLevel.bdf
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