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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-12-21
  • Size : 377kb
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  • Author :周***
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Introduction - If you have any usage issues, please Google them yourself
It ALU design. 7 functions can be performed. This is described in the code. This is a working code. An arithmetic logic unit ALU
Packet file list
(Preview for download)


ALU
...\.cxl.mti_se.version
...\ALU.gise
...\ALU.xise
...\_ngo
...\....\netlist.lst
...\_xmsgs
...\......\map.xmsgs
...\......\ngdbuild.xmsgs
...\......\pn_parser.xmsgs
...\......\xst.xmsgs
...\add.v
...\alu.bld
...\alu.cmd_log
...\alu.fdo
...\alu.lso
...\alu.ngc
...\alu.ngd
...\alu.ngr
...\alu.pcf
...\alu.prj
...\alu.spl
...\alu.stx
...\alu.sym
...\alu.syr
...\alu.udo
...\alu.v
...\alu.xst
...\alu_envsettings.html
...\alu_map.map
...\alu_map.mrp
...\alu_map.ncd
...\alu_map.ngm
...\alu_map.xrpt
...\alu_map_fpga_editor.log
...\alu_ngdbuild.xrpt
...\alu_summary.html
...\alu_summary.xml
...\alu_tb.fdo
...\alu_tb.udo
...\alu_tb.v
...\alu_tb_wave.fdo
...\alu_usage.xml
...\alu_wave.fdo
...\alu_xst.xrpt
...\cla_16.v
...\cla_2.v
...\cla_32.v
...\cla_32_init.v
...\cla_4.v
...\cla_8.v
...\compxlib.cfg
...\compxlib.log
...\g_p.v
...\iseconfig
...\.........\ALU.projectmgr
...\.........\alu.xreport
...\mux4x32.v
...\shift.fdo
...\shift.udo
...\shift.v
...\shift_wave.fdo
...\transcript
...\webtalk_pn.xml
...\work
...\....\_info
...\....\_lib.qdb
...\....\_lib1_0.qdb
...\....\_lib1_0.qpg
...\....\_vmake
...\xlnx_auto_0_xdb
...\...............\cst.xbcd
...\xst
...\...\work
...\...\....\work.sdbl
...\...\....\work.sdbx
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