The fourth round MD5 authentication section contains FPGA one operation I Functions of the source code, using Verilog, synthesis in Quartus

20161203_ii\db\ii.cbx.xml
...........\..\ii.cmp.rdb
...........\..\ii.cmp_merge.kpt
...........\..\ii.db_info
...........\..\ii.eda.qmsg
...........\..\ii.hier_info
...........\..\ii.hif
...........\..\ii.lpc.html
...........\..\ii.lpc.rdb
...........\..\ii.lpc.txt
...........\..\ii.map.bpm
...........\..\ii.map.cdb
...........\..\ii.map.hdb
...........\..\ii.map.kpt
...........\..\ii.map.logdb
...........\..\ii.map.qmsg
...........\..\ii.map.rdb
...........\..\ii.map_bb.cdb
...........\..\ii.map_bb.hdb
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...........\..\ii.pre_map.cdb
...........\..\ii.pre_map.hdb
...........\..\ii.root_partition.map.reg_db.cdb
...........\..\ii.rtlv.hdb
...........\..\ii.rtlv_sg.cdb
...........\..\ii.rtlv_sg_swap.cdb
...........\..\ii.sgdiff.cdb
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...........\..\ii.sld_design_entry.sci
...........\..\ii.sld_design_entry_dsc.sci
...........\..\ii.smart_action.txt
...........\..\ii.syn_hier_info
...........\..\ii.tis_db_list.ddb
...........\..\ii.tmw_info
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_ii.qmsg
...........\ii.done
...........\ii.eda.rpt
...........\ii.flow.rpt
...........\ii.map.rpt
...........\ii.map.summary
...........\ii.qpf
...........\ii.qsf
...........\ii.qws
...........\ii.v
...........\ii.v.bak
...........\ii_nativelink_simulation.rpt
...........\.ncremental_db\compiled_partitions\ii.db_info
...........\..............\...................\ii.root_partition.map.cdb
...........\..............\...................\ii.root_partition.map.dpi
...........\..............\...................\ii.root_partition.map.hbdb.cdb
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...........\..............\...................\ii.root_partition.map.hbdb.sig
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...........\..............\README
...........\simulation\modelsim\ii.vt
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...........\..........\........\ii_run_msim_rtl_verilog.do
...........\..........\........\ii_run_msim_rtl_verilog.do.bak
...........\..........\........\modelsim.ini
...........\..........\........\msim_transcript
...........\..........\........\rtl_work\ii\verilog.prw
...........\..........\........\........\..\verilog.psm
...........\..........\........\........\..\_primary.dat
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...........\..........\........\........\..\_primary.vhd
...........\..........\........\........\.._vlg_tst\verilog.prw
...........\..........\........\........\..........\verilog.psm
...........\..........\........\........\..........\_primary.dat
...........\..........\........\........\..........\_primary.dbs
...........\..........\........\........\..........\_primary.vhd
...........\..........\........\........\_info
...........\..........\........\........\_vmake
...........\..........\........\vsim.wlf
...........\..........\........\rtl_work\ii
...........\..........\........\........\ii_vlg_tst
...........\..........\........\........\_temp
...........\..........\........\rtl_work
...........\incremental_db\compiled_partitions
...........\simulation\modelsim
...........\db
...........\incremental_db
...........\simulation
20161203_ii

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