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Add2bits

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2016-12-29
  • Size : 63kb
  • Downloaded :0次
  • Author :Rid****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
add 2 bits and display result on 7 segment (vhdl)
Packet file list
(Preview for download)


Add2bits\add1bit.vhd
........\add1bit.vhd.bak
........\add2bits.vhd
........\add2bits.vhd.bak
........\Add_7eg.vhd
........\Add_7eg.vhd.bak
........\Add_7seg.qpf
........\Add_7seg.qsf
........\Add_7seg.qws
........\Add_7seg.vhd.bak
........\Add_7seg_assignment_defaults.qdf
........\aff7seg.vhd
........\aff7seg.vhd.bak
........\db\Add_7seg.db_info
........\..\Add_7seg.sld_design_entry.sci
........\..\logic_util_heursitic.dat
........\..\prev_cmp_Add_7seg.qmsg
........\incremental_db\compiled_partitions\Add_7seg.db_info
........\..............\README
........\output_files\Add_7seg.asm.rpt
........\............\Add_7seg.cdf
........\............\Add_7seg.done
........\............\Add_7seg.eda.rpt
........\............\Add_7seg.fit.rpt
........\............\Add_7seg.fit.smsg
........\............\Add_7seg.fit.summary
........\............\Add_7seg.flow.rpt
........\............\Add_7seg.jdi
........\............\Add_7seg.map.rpt
........\............\Add_7seg.map.summary
........\............\Add_7seg.pin
........\............\Add_7seg.pof
........\............\Add_7seg.sof
........\............\Add_7seg.sta.rpt
........\............\Add_7seg.sta.summary
........\simulation\modelsim\Add_7seg.sft
........\..........\........\Add_7seg.vho
........\..........\........\Add_7seg_fast.vho
........\..........\........\Add_7seg_modelsim.xrf
........\..........\........\Add_7seg_vhd.sdo
........\..........\........\Add_7seg_vhd_fast.sdo
........\incremental_db\compiled_partitions
........\simulation\modelsim
........\db
........\incremental_db
........\output_files
........\simulation
Add2bits
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