verilog HDL，design a watch, digital system design

lab16
.....\ise
.....\...\stopwatch
.....\...\.........\.lso
.....\...\.........\stopwatch.bld
.....\...\.........\stopwatch.cmd_log
.....\...\.........\stopwatch.ise
.....\...\.........\stopwatch.ise_ISE_Backup
.....\...\.........\stopwatch.lfp
.....\...\.........\stopwatch.lso
.....\...\.........\stopwatch.ncd
.....\...\.........\stopwatch.ngc
.....\...\.........\stopwatch.ngd
.....\...\.........\stopwatch.ngr
.....\...\.........\stopwatch.ntrc_log
.....\...\.........\stopwatch.pad
.....\...\.........\stopwatch.par
.....\...\.........\stopwatch.pcf
.....\...\.........\stopwatch.prj
.....\...\.........\stopwatch.restore
.....\...\.........\stopwatch.stx
.....\...\.........\stopwatch.syr
.....\...\.........\stopwatch.twr
.....\...\.........\stopwatch.twx
.....\...\.........\stopwatch.unroutes
.....\...\.........\stopwatch.xpi
.....\...\.........\stopwatch.xst
.....\...\.........\stopwatch_dcm.v
.....\...\.........\stopwatch_dcm.xaw
.....\...\.........\stopwatch_dcm_arwz.ucf
.....\...\.........\stopwatch_guide.ncd
.....\...\.........\stopwatch_map.map
.....\...\.........\stopwatch_map.mrp
.....\...\.........\stopwatch_map.ncd
.....\...\.........\stopwatch_map.ngm
.....\...\.........\stopwatch_pad.csv
.....\...\.........\stopwatch_pad.txt
.....\...\.........\stopwatch_prev_built.ngd
.....\...\.........\stopwatch_summary.html
.....\...\.........\stopwatch_summary.xml
.....\...\.........\stopwatch_tb_v.fdo
.....\...\.........\stopwatch_tb_v.udo
.....\...\.........\stopwatch_usage.xml
.....\...\.........\transcript
.....\...\.........\vsim.wlf
.....\...\.........\work
.....\...\.........\....\button_press_unit
.....\...\.........\....\.................\verilog.asm
.....\...\.........\....\.................\_primary.dat
.....\...\.........\....\.................\_primary.vhd
.....\...\.........\....\changer
.....\...\.........\....\.......\verilog.asm
.....\...\.........\....\.......\_primary.dat
.....\...\.........\....\.......\_primary.vhd
.....\...\.........\....\control_1
.....\...\.........\....\.........\verilog.asm
.....\...\.........\....\.........\_primary.dat
.....\...\.........\....\.........\_primary.vhd
.....\...\.........\....\control_2
.....\...\.........\....\.........\verilog.asm
.....\...\.........\....\.........\_primary.dat
.....\...\.........\....\.........\_primary.vhd
.....\...\.........\....\counter_60
.....\...\.........\....\..........\verilog.asm
.....\...\.........\....\..........\_primary.dat
.....\...\.........\....\..........\_primary.vhd
.....\...\.........\....\counter_n
.....\...\.........\....\.........\verilog.asm
.....\...\.........\....\.........\_primary.dat
.....\...\.........\....\.........\_primary.vhd
.....\...\.........\....\decode4_7
.....\...\.........\....\.........\verilog.asm
.....\...\.........\....\.........\_primary.dat
.....\...\.........\....\.........\_primary.vhd
.....\...\.........\....\dff
.....\...\.........\....\...\verilog.asm
.....\...\.........\....\...\_primary.dat
.....\...\.........\....\...\_primary.vhd
.....\...\.........\....\display_unit
.....\...\.........\....\............\verilog.asm
.....\...\.........\....\............\_primary.dat
.....\...\.........\....\............\_primary.vhd
.....\...\.........\....\div
.....\...\.........\....\...\verilog.asm
.....\...\.........\....\...\_primary.dat
.....\...\.........\....\...\_primary.vhd
.....\...\.........\....\encoder3_5
.....\...\.........\....\..........\verilog.asm
.....\...\.........\....\..........\_primary.dat
.....\...\.........\....\..........\_primary.vhd
.....\...\.........\....\glbl
.....\...\.........\....\....\verilog.asm
.....\...\.........\....\....\_primary.dat
.....\...\.........\....\....\_primary.vhd
.....\...\.........\....\mux5_1
.....\...\.........\....\......\verilog.asm
.....\...\.........\....\......\_primary.dat
.....\...\.........\....\......\_primary.vhd
.....\...\.........\....\quiver
.....\...\.........\....\......\verilog.asm

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