| Filename | Size | Update |
|---|
| 100 Power Tips for FPGA Designers - Stavinov | Evgeni\100 Power Tips for FPGA Designers - Stavinov | Evgeni.mobi |
| ....................................................\FBReaderSetup-0.12.10.exe |
| ....................................................\readme.txt |
| ....................................................\src_book\13.14.15.coding\rtl\coding_style.v |
| ....................................................\........\...............\...\simple.v |
| ....................................................\........\...............\...\synth_support.v |
| ....................................................\........\...............\...\tb.v |
| ....................................................\........\...............\synth\isim.cmd |
| ....................................................\........\...............\.....\sim1.wcfg |
| ....................................................\........\...............\.....\sim2.wcfg |
| ....................................................\........\...............\.....\synth.xise |
| ....................................................\........\...............\.....\synth_support.lso |
| ....................................................\........\.6.inference\rtl\inference.v |
| ....................................................\........\............\synth\inference.lso |
| ....................................................\........\............\.....\inference.ptwx |
| ....................................................\........\............\.....\inference.stx |
| ....................................................\........\............\.....\inference.unroutes |
| ....................................................\........\............\.....\inference.xpi |
| ....................................................\........\............\.....\inference_map.mrp |
| ....................................................\........\............\.....\netgen\map\inference_map.sdf |
| ....................................................\........\............\.....\......\...\inference_map.v |
| ....................................................\........\............\.....\......\synthesis\inference_synthesis.v |
| ....................................................\........\............\.....\synth.xise |
| ....................................................\........\.7.mixed_verilog_vhdl\rtl\counter.vhd |
| ....................................................\........\.....................\...\tb.v |
| ....................................................\........\.....................\...\top.v |
| ....................................................\........\.....................\synth\isim.cmd |
| ....................................................\........\.....................\.....\synth.xise |
| ....................................................\........\.....................\.....\top.lso |
| ....................................................\........\.....................\.....\top.ptwx |
| ....................................................\........\.....................\.....\top.stx |
| ....................................................\........\.....................\.....\top_map.mrp |
| ....................................................\........\.8.verilog\rtl\verilog2001.v |
| ....................................................\........\..........\synth\synth.xise |
| ....................................................\........\..........\.....\verilog2001.lso |
| ....................................................\........\..........\.....\verilog2001.stx |
| ....................................................\........\..........\.....\verilog2001_map.mrp |
| ....................................................\........\20.21.clocking\cores\.lso |
| ....................................................\........\..............\.....\blk_mem.v |
| ....................................................\........\..............\.....\blk_mem.xco |
| ....................................................\........\..............\.....\clka_mmcm.v |
| ....................................................\........\..............\.....\clka_mmcm.xco |
| ....................................................\........\.. |