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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-03-04
  • Size : 208kb
  • Downloaded :0次
  • Author :ro***
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Introduction - If you have any usage issues, please Google them yourself
LED Display.
Packet file list
(Preview for download)


LED\designer\impl1\designer.log
...\........\.....\designer_gen_ba.log
...\........\.....\LED.adb
...\........\.....\....dtf\verify.log
...\........\.....\LED.ide_des
...\........\.....\LED.pdb
...\........\.....\LED.pdb.depends
...\........\.....\led.tcl
...\........\.....\led_ba.sdf
...\........\.....\led_ba.v
...\........\.....\LED_fp\$$FlashPro_FPBBALTLPT1.L$$
...\........\.....\......\LED.log
...\........\.....\......\LED.pro
...\........\.....\......\projectData\LED.pdb
...\hdl\LED.v
...\...\waveperl.log
...\LED.prj
...\simulation\modelsim.ini
...\..........\modelsim.ini.sav
...\.martgen\smartgen.aws
...\.ynthesis\.recordref
...\.........\backup\LED.srr
...\.........\LED.areasrr
...\.........\LED.edn
...\.........\LED.fse
...\.........\LED.htm
...\.........\LED.map
...\.........\LED.sap
...\.........\LED.sdf
...\.........\LED.so
...\.........\LED.srd
...\.........\LED.srm
...\.........\LED.srr
...\.........\LED.srs
...\.........\LED.tlg
...\.........\LED_sdc.sdc
...\.........\led_syn.prj
...\.........\run_options.txt
...\.........\stdout.log
...\.........\.yntmp\LED.msg
...\.........\......\LED.plg
...\.........\......\LED_flink.htm
...\.........\......\LED_srr.htm
...\.........\......\LED_toc.htm
...\.........\......\sap.log
...\.........\traplog.tlg
...\viewdraw\vf\project.lst
...\........\viewdraw.ini
...\designer\impl1\LED_fp\projectData
...\........\.....\LED.dtf
...\........\.....\LED_fp
...\........\.....\simulation
...\........\impl1
...\synthesis\backup
...\.........\coreip
...\.........\syntmp
...\viewdraw\sch
...\........\sym
...\........\vf
...\........\wir
...\component
...\constraint
...\coreconsole
...\designer
...\hdl
...\phy_synthesis
...\simulation
...\smartgen
...\stimulus
...\synthesis
...\viewdraw
LED
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