the adder is design by HDL.

Adder\ADDR.prj
.....\component\work\ADDR_TOP\ADDR_TOP.cxf
.....\.........\....\........\ADDR_TOP.sdb
.....\.........\....\........\ADDR_TOP.v
.....\designer\impl1\ADDR_TOP.adb
.....\........\.....\.........dtf\verify.log
.....\........\.....\ADDR_TOP.ide_des
.....\........\.....\ADDR_TOP.pdb
.....\........\.....\ADDR_TOP.pdb.depends
.....\........\.....\ADDR_TOP.tcl
.....\........\.....\........_fp\$$FlashPro_FPBBALTLPT1.L$$
.....\........\.....\...........\ADDR_TOP.log
.....\........\.....\...........\ADDR_TOP.pro
.....\........\.....\...........\projectData\ADDR_TOP.pdb
.....\........\.....\designer.log
.....\hdl\KEY.v
.....\simulation\modelsim.ini
.....\..........\modelsim.ini.sav
.....\.martgen\ADDR\ADDR.cxf
.....\........\....\ADDR.gen
.....\........\....\ADDR.log
.....\........\....\ADDR.v
.....\........\ADDR_TOP_work.ixf
.....\........\ADDR_work.ixf
.....\........\KEY_work.ixf
.....\........\smartgen.aws
.....\.ynthesis\ADDR_TOP.areasrr
.....\.........\ADDR_TOP.edn
.....\.........\ADDR_TOP.fse
.....\.........\ADDR_TOP.htm
.....\.........\ADDR_TOP.map
.....\.........\ADDR_TOP.sap
.....\.........\ADDR_TOP.sdf
.....\.........\ADDR_TOP.so
.....\.........\ADDR_TOP.srd
.....\.........\ADDR_TOP.srm
.....\.........\ADDR_TOP.srr
.....\.........\ADDR_TOP.srs
.....\.........\ADDR_TOP.tlg
.....\.........\ADDR_TOP_sdc.sdc
.....\.........\ADDR_TOP_syn.prj
.....\.........\run_options.txt
.....\.........\stdout.log
.....\.........\.yntmp\ADDR_TOP.msg
.....\.........\......\ADDR_TOP.plg
.....\.........\......\ADDR_TOP_flink.htm
.....\.........\......\ADDR_TOP_srr.htm
.....\.........\......\ADDR_TOP_toc.htm
.....\.........\......\sap.log
.....\viewdraw\vf\project.lst
.....\........\viewdraw.ini
.....\designer\impl1\ADDR_TOP_fp\projectData
.....\component\work\ADDR_TOP
.....\designer\impl1\ADDR_TOP.dtf
.....\........\.....\ADDR_TOP_fp
.....\........\.....\simulation
.....\component\work
.....\designer\impl1
.....\smartgen\ADDR
.....\.ynthesis\backup
.....\.........\coreip
.....\.........\syntmp
.....\viewdraw\sch
.....\........\sym
.....\........\vf
.....\........\wir
.....\component
.....\constraint
.....\coreconsole
.....\designer
.....\hdl
.....\phy_synthesis
.....\simulation
.....\smartgen
.....\stimulus
.....\synthesis
.....\viewdraw
Adder

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