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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-03-04
  • Size : 503kb
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  • Author :ro***
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Introduction - If you have any usage issues, please Google them yourself
The bell code is design by HDL.
Packet file list
(Preview for download)


Bell\BELL.prj
....\designer\impl1\BELL.adb
....\........\.....\.....dtf\verify.log
....\........\.....\BELL.ide_des
....\........\.....\BELL.pdb
....\........\.....\BELL.pdb.depends
....\........\.....\BELL.tcl
....\........\.....\...._fp\$$FlashPro_FPBBALTLPT1.L$$
....\........\.....\.......\BELL.log
....\........\.....\.......\BELL.pro
....\........\.....\.......\projectData\BELL.pdb
....\........\.....\designer.log
....\hdl\BELL.v
....\simulation\modelsim.ini
....\..........\modelsim.ini.sav
....\.martgen\smartgen.aws
....\.ynthesis\.recordref
....\.........\backup\BELL.srr
....\.........\......\key.srr
....\.........\BELL.areasrr
....\.........\BELL.edn
....\.........\BELL.fse
....\.........\BELL.htm
....\.........\BELL.map
....\.........\BELL.sap
....\.........\BELL.sdf
....\.........\BELL.so
....\.........\BELL.srd
....\.........\BELL.srm
....\.........\BELL.srr
....\.........\BELL.srs
....\.........\BELL.tlg
....\.........\BELL_sdc.sdc
....\.........\bell_syn.prj
....\.........\key.areasrr
....\.........\key.edn
....\.........\key.map
....\.........\key.sdf
....\.........\key.so
....\.........\key.srd
....\.........\key.srm
....\.........\key.srr
....\.........\key.srs
....\.........\key.tlg
....\.........\key_sdc.sdc
....\.........\key_syn.prj
....\.........\run_options.txt
....\.........\stdout.log
....\.........\.yntmp\BELL.msg
....\.........\......\BELL.plg
....\.........\......\BELL_flink.htm
....\.........\......\BELL_srr.htm
....\.........\......\BELL_toc.htm
....\.........\......\key.msg
....\.........\......\key.plg
....\.........\......\sap.log
....\.........\traplog.tlg
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\designer\impl1\BELL_fp\projectData
....\........\.....\BELL.dtf
....\........\.....\BELL_fp
....\........\.....\simulation
....\........\impl1
....\synthesis\backup
....\.........\coreip
....\.........\syntmp
....\viewdraw\sch
....\........\sym
....\........\vf
....\........\wir
....\component
....\constraint
....\coreconsole
....\designer
....\hdl
....\phy_synthesis
....\simulation
....\smartgen
....\stimulus
....\synthesis
....\viewdraw
Bell
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