Introduction - If you have any usage issues, please Google them yourself
module sdram_test(
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)