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PowerSum

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-03-14
  • Size : 1kb
  • Downloaded :0次
  • Author :一***
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Introduction - If you have any usage issues, please Google them yourself
The main function of this module is to achieve power and data the unit to solve, that is the real part of the input signal, the imaginary part to solve the square and then put the two together, there are 1024 complex data interfaces within each range cell: clk effective signal and power module input signal, 1bit, active high PowerSumInRe:: clock signal, 50MHz rst_n reset signal, active low PowerSumInEn real power module and the input signal, 8bit PowerSumInIm: power module input signal and imaginary section, 8bit PowerSumOut: power and the module output signal, namely power and, 16bit PowerSumOutEn: power and the module output signal is valid, 1bit, active high
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PowerSum.v
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