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01_Counter_Design

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-03-17
  • Size : 2.86mb
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  • Author :胡****
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Introduction - If you have any usage issues, please Google them yourself
FPGA-based control of the 4-bit counter, has been debugging simulation available
Packet file list
(Preview for download)


01_Counter_Design\Counter_design.qpf
.................\Counter_design.qsf
.................\Counter_design.qws
.................\Counter_design.v
.................\Counter_design.v.bak
.................\db\Counter_design.asm.qmsg
.................\..\Counter_design.asm.rdb
.................\..\Counter_design.asm_labs.ddb
.................\..\Counter_design.cbx.xml
.................\..\Counter_design.cmp.bpm
.................\..\Counter_design.cmp.cdb
.................\..\Counter_design.cmp.hdb
.................\..\Counter_design.cmp.idb
.................\..\Counter_design.cmp.kpt
.................\..\Counter_design.cmp.logdb
.................\..\Counter_design.cmp.rdb
.................\..\Counter_design.cmp_merge.kpt
.................\..\Counter_design.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.................\..\Counter_design.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
.................\..\Counter_design.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.................\..\Counter_design.db_info
.................\..\Counter_design.eda.qmsg
.................\..\Counter_design.fit.qmsg
.................\..\Counter_design.hier_info
.................\..\Counter_design.hif
.................\..\Counter_design.ipinfo
.................\..\Counter_design.lpc.html
.................\..\Counter_design.lpc.rdb
.................\..\Counter_design.lpc.txt
.................\..\Counter_design.map.ammdb
.................\..\Counter_design.map.bpm
.................\..\Counter_design.map.cdb
.................\..\Counter_design.map.hdb
.................\..\Counter_design.map.kpt
.................\..\Counter_design.map.logdb
.................\..\Counter_design.map.qmsg
.................\..\Counter_design.map.rdb
.................\..\Counter_design.map_bb.cdb
.................\..\Counter_design.map_bb.hdb
.................\..\Counter_design.map_bb.logdb
.................\..\Counter_design.pplq.rdb
.................\..\Counter_design.pre_map.hdb
.................\..\Counter_design.pti_db_list.ddb
.................\..\Counter_design.root_partition.map.reg_db.cdb
.................\..\Counter_design.routing.rdb
.................\..\Counter_design.rpp.qmsg
.................\..\Counter_design.rtlv.hdb
.................\..\Counter_design.rtlv_sg.cdb
.................\..\Counter_design.rtlv_sg_swap.cdb
.................\..\Counter_design.sgate.rvd
.................\..\Counter_design.sgate_sm.rvd
.................\..\Counter_design.sgdiff.cdb
.................\..\Counter_design.sgdiff.hdb
.................\..\Counter_design.sld_design_entry.sci
.................\..\Counter_design.sld_design_entry_dsc.sci
.................\..\Counter_design.smart_action.txt
.................\..\Counter_design.sta.qmsg
.................\..\Counter_design.sta.rdb
.................\..\Counter_design.sta_cmp.8_slow_1200mv_85c.tdb
.................\..\Counter_design.syn_hier_info
.................\..\Counter_design.tiscmp.fastest_slow_1200mv_0c.ddb
.................\..\Counter_design.tiscmp.fastest_slow_1200mv_85c.ddb
.................\..\Counter_design.tiscmp.fast_1200mv_0c.ddb
.................\..\Counter_design.tiscmp.slow_1200mv_0c.ddb
.................\..\Counter_design.tiscmp.slow_1200mv_85c.ddb
.................\..\Counter_design.tis_db_list.ddb
.................\..\Counter_design.tmw_info
.................\..\Counter_design.vpr.ammdb
.................\..\logic_util_heursitic.dat
.................\..\prev_cmp_Counter_design.qmsg
.................\incremental_db\compiled_partitions\Counter_design.db_info
.................\..............\...................\Counter_design.root_partition.cmp.ammdb
.................\..............\...................\Counter_design.root_partition.cmp.cdb
.................\..............\...................\Counter_design.root_partition.cmp.dfp
.................\..............\...................\Counter_design.root_partition.cmp.hdb
.................\..............\...................\Counter_design.root_partition.cmp.kpt
.................\..............\...................\Counter_design.root_partition.cmp.logdb
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