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project_zynq

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-03-17
  • Size : 18.81mb
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  • Author :王***
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Introduction - If you have any usage issues, please Google them yourself
Use ZYNQ to create a control peripheral MicroBlaze
Packet file list
(Preview for download)


project_zynq\.Xil
............\project_zynq.cache
............\..................\compile_simlib
............\..................\..............\activehdl
............\..................\..............\ies
............\..................\..............\modelsim
............\..................\..............\questa
............\..................\..............\riviera
............\..................\..............\vcs
............\..................\wt
............\..................\..\java_command_handlers.wdf
............\..................\..\project.wpc
............\..................\..\synthesis.wdf
............\..................\..\synthesis_details.wdf
............\..................\..\webtalk_pa.xml
............\project_zynq.hw
............\...............\project_zynq.lpr
............\project_zynq.ip_user_files
............\..........................\bd
............\..........................\..\system
............\..........................\..\......\hdl
............\..........................\..\......\...\system.v
............\..........................\..\......\ip
............\..........................\..\......\..\system_processing_system7_0_0
............\..........................\..\......\..\.............................\sim
............\..........................\..\......\..\.............................\...\system_processing_system7_0_0.v
............\..........................\ipstatic
............\..........................\........\processing_system7_bfm_v2_0
............\..........................\........\...........................\hdl
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_apis.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_axi_acp.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_axi_gp.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_axi_hp.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_local_params.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_reg_init.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_reg_params.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_5_unused_ports.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_afi_slave.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_arb_hp0_1.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_arb_hp2_3.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_arb_rd.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_arb_rd_4.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_arb_wr.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_arb_wr_4.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_axi_master.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_axi_slave.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_ddrc.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_fmsw_gp.v
............\..........................\........\...........................\...\processing_system7_bfm_v2_0_gen_clock.v
............\..........................\........\...........................\...\pr
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