Creation of FPGA-based device. circuit represents a simple device, containing D Flip-Flop with optional asynchronous Reset inputs and AND logic gate

project_1
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.........\...............\compile_simlib
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.........\...............\..............\riviera
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.........\...............\wt
.........\...............\..\gui_resources.wdf
.........\...............\..\java_command_handlers.wdf
.........\...............\..\project.wpc
.........\...............\..\synthesis.wdf
.........\...............\..\synthesis_details.wdf
.........\...............\..\webtalk_pa.xml
.........\...............\..\xsim.wdf
.........\project_1.hw
.........\............\project_1.lpr
.........\project_1.ip_user_files
.........\.......................\bd
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.........\.......................\..\.........\..\schematic_and_comp_0_0
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.........\.......................\..\.........\..\schematic_fdc_comp_0_0
.........\.......................\..\.........\..\......................\sim
.........\.......................\..\.........\..\......................\...\schematic_fdc_comp_0_0.vhd
.........\.......................\README.txt
.........\.......................\sim_scripts
.........\.......................\...........\schematic
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.........\.......................\...........\.........\.........\compile.do
.........\.......................\...........\.........\.........\file_info.txt
.........\.......................\...........\.........\.........\README.txt
.........\.......................\...........\.........\.........\schematic.sh
.........\.......................\...........\.........\.........\schematic.udo
.........\.......................\...........\.........\.........\simulate.do
.........\.......................\...........\.........\.........\wave.do
.........\.......................\...........\.........\ies
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.........\.......................\...........\.........\...\run.f
.........\.......................\...........\.........\...\schematic.sh
.........\.......................\...........\.........\modelsim
.........\.......................\...........\.........\........\compile.do
.........\.......................\...........\.........\........\file_info.txt
.........\.......................\...........\.........\........\README.txt
.........\.......................\...........\.........\........\schematic.sh
.........\.......................\...........\.........\........\schematic.udo
.........\.......................\...........\.........\........\simulate.do
.........\.......................\...........\.........\........\wave.do
.........\.......................\...........\.........\questa
.........\.......................\...........\.........\......\compile.do
.........\.......................\...........\.........\......\elaborate.do
.........\.......................\...........\.........\......\file_info.txt
.........\.......................\...........\.........\......\README.txt
.........\.......................\...........\.........\......\schematic.sh
.........\.......................\...........\.........\......\schematic.udo
.........\.......................\...........\.........\......\simulate.do
.........\.......................\...........\.........\......\wave.do
.........\.......................\...........\.........\README.txt
.........\.......................\...........\.........\riviera
.........\..................

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