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PCIe_Lab

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-03-29
  • Size : 5.92mb
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Introduction - If you have any usage issues, please Google them yourself
PCIe lab It is said that it is a seminar information, have a try if you need
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PCIe_Lab\.qsys_edit\filters.xml
........\..........\preferences.xml
........\altgx_reconfig.v
........\c4gx_qsys\synthesis\c4gx_qsys.qip
........\.........\.........\c4gx_qsys.v
........\.........\.........\submodules\altera_avalon_mm_bridge.v
........\.........\.........\..........\altera_avalon_sc_fifo.v
........\.........\.........\..........\altera_avalon_st_pipeline_base.v
........\.........\.........\..........\altera_avalon_st_pipeline_stage.sv
........\.........\.........\..........\altera_irq_clock_crosser.sv
........\.........\.........\..........\altera_merlin_arbitrator.sv
........\.........\.........\..........\altera_merlin_burst_adapter.sv
........\.........\.........\..........\altera_merlin_burst_uncompressor.sv
........\.........\.........\..........\altera_merlin_master_agent.sv
........\.........\.........\..........\altera_merlin_master_translator.sv
........\.........\.........\..........\altera_merlin_slave_agent.sv
........\.........\.........\..........\altera_merlin_slave_translator.sv
........\.........\.........\..........\altera_merlin_traffic_limiter.sv
........\.........\.........\..........\altera_merlin_width_adapter.sv
........\.........\.........\..........\altera_pcie_hard_ip_reset_controller.v
........\.........\.........\..........\altera_pci_express.sdc
........\.........\.........\..........\altera_reset_controller.sdc
........\.........\.........\..........\altera_reset_controller.v
........\.........\.........\..........\altera_reset_synchronizer.v
........\.........\.........\..........\altpcie_hip_pipen1b.v
........\.........\.........\..........\altpcie_pipe_interface.v
........\.........\.........\..........\altpcie_pll_100_250.v
........\.........\.........\..........\altpcie_pll_125_250.v
........\.........\.........\..........\altpcie_rs_serdes.v
........\.........\.........\..........\byte_enable_generator.v
........\.........\.........\..........\c4gx_qsys_addr_router.sv
........\.........\.........\..........\c4gx_qsys_addr_router_001.sv
........\.........\.........\..........\c4gx_qsys_addr_router_002.sv
........\.........\.........\..........\c4gx_qsys_cmd_xbar_demux.sv
........\.........\.........\..........\c4gx_qsys_cmd_xbar_demux_001.sv
........\.........\.........\..........\c4gx_qsys_cmd_xbar_demux_002.sv
........\.........\.........\..........\c4gx_qsys_cmd_xbar_mux_003.sv
........\.........\.........\..........\c4gx_qsys_cmd_xbar_mux_004.sv
........\.........\.........\..........\c4gx_qsys_dma_0.v
........\.........\.........\..........\c4gx_qsys_id_router.sv
........\.........\.........\..........\c4gx_qsys_id_router_001.sv
........\.........\.........\..........\c4gx_qsys_id_router_003.sv
........\.........\.........\..........\c4gx_qsys_id_router_004.sv
........\.........\.........\..........\c4gx_qsys_irq_mapper.sv
........\.........\.........\..........\c4gx_qsys_onchip_memory_0.hex
........\.........\.........\..........\c4gx_qsys_onchip_memory_0.v
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0.v
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0_addr_router.sv
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0_altgx_internal.v
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0_cmd_xbar_demux.sv
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0_id_router.sv
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0_rsp_xbar_demux.sv
........\.........\.........\..........\c4gx_qsys_pcie_hard_ip_0_rsp_xbar_mux.sv
........\.........\.........\..........\c4gx_qsys_rsp_xbar_demux.sv
........\.........\.........\..........\c4gx_qsys_rsp_xbar_demux_003.sv
........\.........\.........\..........\c4gx_qsys_rsp_xbar_mux.sv
........\.........\.........\..........\c4gx_qsys_rsp_xbar_mux_002.sv
........\.........\.........\..........\csr_block.v
........\.........\.........\..........\descriptor_buffers.v
........\.........\.........\..........\dispatcher.v
........\.........\.........\..........\fifo_with_byteenables.v
........\.........\.........\..........\MM_to_ST_Adapter.v
....
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