Adjust digital display files for CYCLONE II development board, using VHDL language, it is very suitable for transplantation into digital clock to realize the function of regulation time. Simple multi-module design.

FPGA_exp2
.........\c5_pin_model_dump.txt
.........\cio_dump_disallowed_lists.echo
.........\convert3to8.vhd
.........\counter.vhd
.........\db
.........\..\FPGA_exp2.asm.qmsg
.........\..\FPGA_exp2.asm.rdb
.........\..\FPGA_exp2.cbx.xml
.........\..\FPGA_exp2.cmp.bpm
.........\..\FPGA_exp2.cmp.cdb
.........\..\FPGA_exp2.cmp.hdb
.........\..\FPGA_exp2.cmp.idb
.........\..\FPGA_exp2.cmp.kpt
.........\..\FPGA_exp2.cmp.logdb
.........\..\FPGA_exp2.cmp.rdb
.........\..\FPGA_exp2.cmp_merge.kpt
.........\..\FPGA_exp2.cyclonev_io_sim_cache.ff_0c_fast.hsd
.........\..\FPGA_exp2.cyclonev_io_sim_cache.ff_85c_fast.hsd
.........\..\FPGA_exp2.cyclonev_io_sim_cache.ss_0c_slow.hsd
.........\..\FPGA_exp2.cyclonev_io_sim_cache.ss_85c_slow.hsd
.........\..\FPGA_exp2.db_info
.........\..\FPGA_exp2.eda.qmsg
.........\..\FPGA_exp2.fit.qmsg
.........\..\FPGA_exp2.hier_info
.........\..\FPGA_exp2.hif
.........\..\FPGA_exp2.ipinfo
.........\..\FPGA_exp2.lpc.html
.........\..\FPGA_exp2.lpc.rdb
.........\..\FPGA_exp2.lpc.txt
.........\..\FPGA_exp2.map.ammdb
.........\..\FPGA_exp2.map.bpm
.........\..\FPGA_exp2.map.cdb
.........\..\FPGA_exp2.map.hdb
.........\..\FPGA_exp2.map.kpt
.........\..\FPGA_exp2.map.logdb
.........\..\FPGA_exp2.map.qmsg
.........\..\FPGA_exp2.map.rdb
.........\..\FPGA_exp2.map_bb.cdb
.........\..\FPGA_exp2.map_bb.hdb
.........\..\FPGA_exp2.map_bb.logdb
.........\..\FPGA_exp2.pplq.rdb
.........\..\FPGA_exp2.pre_map.hdb
.........\..\FPGA_exp2.pti_db_list.ddb
.........\..\FPGA_exp2.root_partition.map.reg_db.cdb
.........\..\FPGA_exp2.routing.rdb
.........\..\FPGA_exp2.rpp.qmsg
.........\..\FPGA_exp2.rtlv.hdb
.........\..\FPGA_exp2.rtlv_sg.cdb
.........\..\FPGA_exp2.rtlv_sg_swap.cdb
.........\..\FPGA_exp2.sgate.rvd
.........\..\FPGA_exp2.sgate_sm.rvd
.........\..\FPGA_exp2.sld_design_entry.sci
.........\..\FPGA_exp2.sld_design_entry_dsc.sci
.........\..\FPGA_exp2.smart_action.txt
.........\..\FPGA_exp2.sta.qmsg
.........\..\FPGA_exp2.sta.rdb
.........\..\FPGA_exp2.sta_cmp.8_slow_1100mv_85c.tdb
.........\..\FPGA_exp2.syn_hier_info
.........\..\FPGA_exp2.tiscmp.fastest_slow_1100mv_0c.ddb
.........\..\FPGA_exp2.tiscmp.fastest_slow_1100mv_85c.ddb
.........\..\FPGA_exp2.tiscmp.fast_1100mv_0c.ddb
.........\..\FPGA_exp2.tiscmp.fast_1100mv_85c.ddb
.........\..\FPGA_exp2.tiscmp.slow_1100mv_0c.ddb
.........\..\FPGA_exp2.tiscmp.slow_1100mv_85c.ddb
.........\..\FPGA_exp2.tis_db_list.ddb
.........\..\FPGA_exp2.tmw_info
.........\..\FPGA_exp2.vpr.ammdb
.........\..\logic_util_heursitic.dat
.........\..\prev_cmp_FPGA_exp2.qmsg
.........\decoder47.vhd
.........\div20Mto400.vhd
.........\div400to1.vhd
.........\FPGA_exp2.qpf
.........\FPGA_exp2.qsf
.........\FPGA_exp2.qws
.........\fpga_exp2.vhd
.........\hc_output
.........\.........\FPGA_exp2.names_drv_tbl
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\FPGA_exp2.db_info
.........\..............\...................\FPGA_exp2.root_partition.cmp.ammdb
.........\..............\...................\FPGA_exp2.root_partition.cmp.cdb
.........\..............\...................\FPGA_exp2.root_partition.cmp.dfp
.........\..............\...................\FPGA_exp2.root_partition.cmp.hbdb.cdb
.........\..............\...................\FPGA_exp2.root_partition.cmp.hbdb.hdb
.........\..............\...................\FPGA_exp2.root_partition.cmp.hbdb.sig
.........\..............\...................\FPGA_exp2.root_partition.cmp.hdb
.........\..............\...................\FPGA_exp2.root_partition.cmp.kpt
.........\..............\...................\FPGA_exp2.root_partition.cmp.logdb
.........\..............\...................\FPGA_exp2.root_partition.cmp.rcfdb
.........\..............\...................\FPGA_exp2.root_partition.map.cdb
.........\..............\...................\FPGA_exp2.root_partition.map.dpi
.........\..............\...................\FPGA_exp2.root_partition.map.hbdb.cdb
.........\..............\...................\FPGA_exp2.root_partition.map.hbdb.hb_info
.........\..............\...................\FP

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