FPGA control program for collecting and storing the sensor. Stored by the RAM.

51
..\FPGA_TR.c
AD_collect.bsf
AD_collect.v
AD_collect.v.bak
Block_1.bdf
Block_1.v
Block_1.v.bak
clock_divider.bsf
clock_divider.v
clock_divider.v.bak
db
..\altsyncram_cnm1.tdf
..\altsyncram_mjm1.tdf
..\altsyncram_pom1.tdf
..\decode_ara.tdf
..\logic_util_heursitic.dat
..\mux_9nb.tdf
..\Phase.db_info
..\prev_cmp_Phase.qmsg
greybox_tmp
...........\cbx_args.txt
incremental_db
..............\compiled_partitions
..............\...................\Phase.root_partition.cmp.dfp
..............\...................\Phase.root_partition.cmp.kpt
..............\...................\Phase.root_partition.cmp.logdb
..............\...................\Phase.root_partition.map.dpi
..............\...................\Phase.root_partition.map.kpt
..............\README
MCU_51.inc
MCU_51.v
MCU_51.v.bak
Phase.asm.rpt
Phase.cdf
Phase.done
Phase.eda.rpt
Phase.fit.rpt
Phase.fit.smsg
Phase.fit.summary
Phase.flow.rpt
Phase.map.rpt
Phase.map.smsg
Phase.map.summary
Phase.pin
Phase.qpf
Phase.qsf
Phase.qws
Phase.sof
Phase.sta.rpt
Phase.sta.summary
Phase_assignment_defaults.qdf
Phase_nativelink_simulation.rpt
RAM1.bsf
RAM1.qip
RAM1.v
RAM1_bb.v
RAM1_wave0.jpg
RAM1_wave1.jpg
simulation
..........\modelsim
..........\........\Block_1.vt
..........\........\Block_1.vt.bak
..........\........\modelsim.ini
..........\........\msim_transcript
..........\........\Phase.sft
..........\........\Phase.vo
..........\........\Phase_8_1200mv_0c_slow.vo
..........\........\Phase_8_1200mv_0c_v_slow.sdo
..........\........\Phase_8_1200mv_85c_slow.vo
..........\........\Phase_8_1200mv_85c_v_slow.sdo
..........\........\Phase_min_1200mv_0c_fast.vo
..........\........\Phase_min_1200mv_0c_v_fast.sdo
..........\........\Phase_modelsim.xrf
..........\........\Phase_run_msim_rtl_verilog.do
..........\........\Phase_run_msim_rtl_verilog.do.bak
..........\........\Phase_v.sdo
..........\........\rtl_work
..........\........\........\@a@d_collect
..........\........\........\............\_primary.dat
..........\........\........\............\_primary.vhd
..........\........\........\............\verilog.asm
..........\........\........\@block1
..........\........\........\.......\_primary.dat
..........\........\........\.......\_primary.vhd
..........\........\........\.......\verilog.asm
..........\........\........\@block1_vlg_tst
..........\........\........\...............\_primary.dat
..........\........\........\...............\_primary.vhd
..........\........\........\...............\verilog.asm
..........\........\........\@m@c@u_51
..........\........\........\.........\_primary.dat
..........\........\........\.........\_primary.vhd
..........\........\........\.........\verilog.asm
..........\........\........\@r@a@m1
..........\........\........\.......\_primary.dat
..........\........\........\.......\_primary.vhd
..........\........\........\.......\verilog.asm
..........\........\........\_info
..........\........\........\_temp

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．