Based on Quartus II 13.0 FirFullSerial basic engineering design process, it contains a detailed doc document

3_FirFullSerial
...............\core
...............\....\adder.v
...............\....\clock_gen.v
...............\....\mult.v
...............\....\wave_gen.mif
...............\....\wave_rom.qip
...............\....\wave_rom.v
...............\....\wave_rom.v.bak
...............\dev
...............\...\FirFullSerial.qpf
...............\...\PLLJ_PLLSPE_INFO.txt
...............\...\adder.qip
...............\...\clock_gen.qip
...............\...\db
...............\...\..\FirFullSerial.map_bb.logdb
...............\...\..\add_sub_1nh.tdf
...............\...\..\add_sub_7jh.tdf
...............\...\..\altsyncram_2124.tdf
...............\...\..\altsyncram_8nc1.tdf
...............\...\..\altsyncram_cjc1.tdf
...............\...\..\altsyncram_ejc1.tdf
...............\...\..\altsyncram_jsc1.tdf
...............\...\..\altsyncram_qlc1.tdf
...............\...\..\clock_gen_altpll.v
...............\...\..\cmpr_ngc.tdf
...............\...\..\cmpr_rgc.tdf
...............\...\..\cmpr_sgc.tdf
...............\...\..\cntr_23j.tdf
...............\...\..\cntr_fgi.tdf
...............\...\..\cntr_ggi.tdf
...............\...\..\cntr_m9j.tdf
...............\...\..\decode_dvf.tdf
...............\...\..\design_top.asm.qmsg
...............\...\..\design_top.asm.rdb
...............\...\..\design_top.asm_labs.ddb
...............\...\..\design_top.autoh_e40e1.map.reg_db.cdb
...............\...\..\design_top.autos_3e921.map.reg_db.cdb
...............\...\..\design_top.cbx.xml
...............\...\..\design_top.cmp.bpm
...............\...\..\design_top.cmp.cdb
...............\...\..\design_top.cmp.hdb
...............\...\..\design_top.cmp.idb
...............\...\..\design_top.cmp.kpt
...............\...\..\design_top.cmp.logdb
...............\...\..\design_top.cmp.rdb
...............\...\..\design_top.cmp_merge.kpt
...............\...\..\design_top.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
...............\...\..\design_top.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
...............\...\..\design_top.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
...............\...\..\design_top.db_info
...............\...\..\design_top.eda.qmsg
...............\...\..\design_top.fit.qmsg
...............\...\..\design_top.hier_info
...............\...\..\design_top.hif
...............\...\..\design_top.ipinfo
...............\...\..\design_top.lpc.html
...............\...\..\design_top.lpc.rdb
...............\...\..\design_top.lpc.txt
...............\...\..\design_top.map.ammdb
...............\...\..\design_top.map.bpm
...............\...\..\design_top.map.cdb
...............\...\..\design_top.map.hdb
...............\...\..\design_top.map.kpt
...............\...\..\design_top.map.qmsg
...............\...\..\design_top.map.rdb
...............\...\..\design_top.map_bb.cdb
...............\...\..\design_top.map_bb.hdb
...............\...\..\design_top.pplq.rdb
...............\...\..\design_top.pre_map.hdb
...............\...\..\design_top.pti_db_list.ddb
...............\...\..\design_top.root_partition.map.reg_db.cdb
...............\...\..\design_top.routing.rdb
...............\...\..\design_top.rtlv.hdb
...............\...\..\design_top.rtlv_sg.cdb
...............\...\..\design_top.rtlv_sg_swap.cdb
...............\...\..\design_top.sgdiff.cdb
...............\...\..\design_top.sgdiff.hdb
...............\...\..\design_top.sld_design_entry.sci
...............\...\..\design_top.sld_design_entry_dsc.sci
...............\...\..\design_top.smart_action.txt
...............\...\..\design_top.sta.qmsg
...............\...\..\design_top.sta.rdb
...............\...\..\design_top.sta_cmp.8_slow_1200mv_85c.tdb
...............\...\..\design_top.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
...............\...\..\design_top.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
...............\...\..\design_top.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
...............\...\..\design_top.syn_hier_info
...............\...\..\design_top.tis_db_list.ddb
...............\...\..\design_top.tiscmp.fast_1200mv_0c.ddb
...............\...\..\design_top.tiscmp.fastest_slow_1200mv_0c

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