The fpga- phase-locked loop using phase-locked loop experiment, development environment for the Quartus II

10_PLL
......\FPGA
......\....\db
......\....\greybox_tmp
......\....\...........\cbx_args.txt
......\....\iCore3.tcl
......\....\incremental_db
......\....\..............\compiled_partitions
......\....\..............\...................\PLL.autoh_e40e1.map.cdb
......\....\..............\...................\PLL.autoh_e40e1.map.dpi
......\....\..............\...................\PLL.autoh_e40e1.map.hdb
......\....\..............\...................\PLL.autoh_e40e1.map.kpt
......\....\..............\...................\PLL.autoh_e40e1.map.logdb
......\....\..............\...................\PLL.autos_3e921.map.cdb
......\....\..............\...................\PLL.autos_3e921.map.dpi
......\....\..............\...................\PLL.autos_3e921.map.hdb
......\....\..............\...................\PLL.autos_3e921.map.kpt
......\....\..............\...................\PLL.autos_3e921.map.logdb
......\....\..............\...................\PLL.db_info
......\....\..............\...................\PLL.root_partition.cmp.ammdb
......\....\..............\...................\PLL.root_partition.cmp.cdb
......\....\..............\...................\PLL.root_partition.cmp.dfp
......\....\..............\...................\PLL.root_partition.cmp.hdb
......\....\..............\...................\PLL.root_partition.cmp.logdb
......\....\..............\...................\PLL.root_partition.cmp.rcfdb
......\....\..............\...................\PLL.root_partition.map.cdb
......\....\..............\...................\PLL.root_partition.map.dpi
......\....\..............\...................\PLL.root_partition.map.hbdb.cdb
......\....\..............\...................\PLL.root_partition.map.hbdb.hb_info
......\....\..............\...................\PLL.root_partition.map.hbdb.hdb
......\....\..............\...................\PLL.root_partition.map.hbdb.sig
......\....\..............\...................\PLL.root_partition.map.hdb
......\....\..............\...................\PLL.root_partition.map.kpt
......\....\..............\README
......\....\my_pll.qip
......\....\output_files
......\....\............\greybox_tmp
......\....\............\...........\cbx_args.txt
......\....\............\my_pll.qip
......\....\............\PLL.asm.rpt
......\....\............\PLL.done
......\....\............\PLL.eda.rpt
......\....\............\PLL.fit.rpt
......\....\............\PLL.fit.smsg
......\....\............\PLL.fit.summary
......\....\............\PLL.flow.rpt
......\....\............\PLL.jdi
......\....\............\PLL.map.rpt
......\....\............\PLL.map.smsg
......\....\............\PLL.map.summary
......\....\............\PLL.pin
......\....\............\PLL.sof
......\....\............\PLL.sta.rpt
......\....\............\PLL.sta.summary
......\....\............\stp1.stp
......\....\PLL.qpf
......\....\PLL.qsf
......\....\PLL.qws
......\....\PLLJ_PLLSPE_INFO.txt
......\....\simulation
......\....\..........\modelsim
......\....\..........\........\PLL.sft
......\....\..........\........\PLL.vo
......\....\..........\........\PLL_8_1200mv_0c_slow.vo
......\....\..........\........\PLL_8_1200mv_0c_v_slow.sdo
......\....\..........\........\PLL_8_1200mv_85c_slow.vo
......\....\..........\........\PLL_8_1200mv_85c_v_slow.sdo
......\....\..........\........\PLL_min_1200mv_0c_fast.vo
......\....\..........\........\PLL_min_1200mv_0c_v_fast.sdo
......\....\..........\........\PLL_modelsim.xrf
......\....\..........\........\PLL_v.sdo
......\....\src
......\....\...\greybox_tmp
......\....\...\...........\cbx_args.txt
......\....\...\my_pll.ppf
......\....\...\my_pll.qip
......\....\...\my_pll.v
......\....\...\my_pll_bb.v
......\....\...\PLL.v
iCore3_FPGA_实验指导书十
........................\iCore3_FPGA_实验指导书十.pdf

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