FPGA code, using Verilog HDL language is converted into a binary 4 bit BCD code. The principle is Shift-Add-3 .

Bin2BCD
.......\add3.v
.......\add3.v.bak
.......\Bin2BCD.cr.mti
.......\Bin2BCD.mpf
.......\Bin2BCD.qpf
.......\Bin2BCD.qsf
.......\Bin2BCD.qws
.......\Bin2BCD.v
.......\Bin2BCD.v.bak
.......\c5_pin_model_dump.txt
.......\db
.......\..\.cmp.kpt
.......\..\Bin2BCD.analyze_file.qmsg
.......\..\Bin2BCD.asm.qmsg
.......\..\Bin2BCD.asm.rdb
.......\..\Bin2BCD.cbx.xml
.......\..\Bin2BCD.cmp.idb
.......\..\Bin2BCD.cmp.rdb
.......\..\Bin2BCD.cmp_merge.kpt
.......\..\Bin2BCD.cyclonev_io_sim_cache.ff_0c_fast.hsd
.......\..\Bin2BCD.cyclonev_io_sim_cache.ff_85c_fast.hsd
.......\..\Bin2BCD.cyclonev_io_sim_cache.tt_0c_slow.hsd
.......\..\Bin2BCD.cyclonev_io_sim_cache.tt_85c_slow.hsd
.......\..\Bin2BCD.db_info
.......\..\Bin2BCD.eda.qmsg
.......\..\Bin2BCD.fit.qmsg
.......\..\Bin2BCD.hier_info
.......\..\Bin2BCD.hif
.......\..\Bin2BCD.ipinfo
.......\..\Bin2BCD.lpc.html
.......\..\Bin2BCD.lpc.rdb
.......\..\Bin2BCD.lpc.txt
.......\..\Bin2BCD.map.ammdb
.......\..\Bin2BCD.map.bpm
.......\..\Bin2BCD.map.cdb
.......\..\Bin2BCD.map.hdb
.......\..\Bin2BCD.map.kpt
.......\..\Bin2BCD.map.logdb
.......\..\Bin2BCD.map.qmsg
.......\..\Bin2BCD.map.rdb
.......\..\Bin2BCD.map_bb.cdb
.......\..\Bin2BCD.map_bb.hdb
.......\..\Bin2BCD.map_bb.logdb
.......\..\Bin2BCD.npp.qmsg
.......\..\Bin2BCD.pre_map.hdb
.......\..\Bin2BCD.pti_db_list.ddb
.......\..\Bin2BCD.root_partition.map.reg_db.cdb
.......\..\Bin2BCD.routing.rdb
.......\..\Bin2BCD.rtlv.hdb
.......\..\Bin2BCD.rtlv_sg.cdb
.......\..\Bin2BCD.rtlv_sg_swap.cdb
.......\..\Bin2BCD.sgate.nvd
.......\..\Bin2BCD.sgate_sm.nvd
.......\..\Bin2BCD.sld_design_entry.sci
.......\..\Bin2BCD.sld_design_entry_dsc.sci
.......\..\Bin2BCD.smart_action.txt
.......\..\Bin2BCD.sta.qmsg
.......\..\Bin2BCD.sta.rdb
.......\..\Bin2BCD.tiscmp.fast_1100mv_0c.ddb
.......\..\Bin2BCD.tiscmp.fast_1100mv_85c.ddb
.......\..\Bin2BCD.tiscmp.slow_1100mv_0c.ddb
.......\..\Bin2BCD.tiscmp.slow_1100mv_85c.ddb
.......\..\Bin2BCD.tis_db_list.ddb
.......\..\Bin2BCD.vpr.ammdb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_Bin2BCD.qmsg
.......\fulladder.v
.......\fulladder.v.bak
.......\hc_output
.......\.........\Bin2BCD.names_drv_tbl
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\Bin2BCD.db_info
.......\..............\...................\Bin2BCD.root_partition.cmp.ammdb
.......\..............\...................\Bin2BCD.root_partition.cmp.cdb
.......\..............\...................\Bin2BCD.root_partition.cmp.dfp
.......\..............\...................\Bin2BCD.root_partition.cmp.hbdb.cdb
.......\..............\...................\Bin2BCD.root_partition.cmp.hbdb.hdb
.......\..............\...................\Bin2BCD.root_partition.cmp.hbdb.sig
.......\..............\...................\Bin2BCD.root_partition.cmp.hdb
.......\..............\...................\Bin2BCD.root_partition.cmp.logdb
.......\..............\...................\Bin2BCD.root_partition.cmp.rcfdb
.......\..............\...................\Bin2BCD.root_partition.map.cdb
.......\..............\...................\Bin2BCD.root_partition.map.dpi
.......\..............\...................\Bin2BCD.root_partition.map.hbdb.cdb
.......\..............\...................\Bin2BCD.root_partition.map.hbdb.hb_info
.......\..............\...................\Bin2BCD.root_partition.map.hbdb.hdb
.......\..............\...................\Bin2BCD.root_partition.map.hbdb.sig
.......\..............\...................\Bin2BCD.root_partition.map.hdb
.......\..............\...................\Bin2BCD.root_partition.map.kpt
.......\..............\README
.......\O.v
.......\output_files
.......\............\Bin2BCD.asm.rpt
.......\............\Bin2BCD.done
.......\............\Bin2BCD.eda.rpt
.......\............\Bin2BCD.fit.rpt
.......\............\Bin2BCD.fit.smsg
.......\............\Bin2BCD.fit.summary

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