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Verilog-trafficLights

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-04-23
  • Size : 443kb
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  • Author :盛***
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exp3
....\db
....\..\exp3.amm.cdb
....\..\exp3.asm.qmsg
....\..\exp3.asm.rdb
....\..\exp3.asm_labs.ddb
....\..\exp3.cbx.xml
....\..\exp3.cmp.bpm
....\..\exp3.cmp.cdb
....\..\exp3.cmp.hdb
....\..\exp3.cmp.kpt
....\..\exp3.cmp.logdb
....\..\exp3.cmp.rdb
....\..\exp3.cmp0.ddb
....\..\exp3.cmp1.ddb
....\..\exp3.cmp_merge.kpt
....\..\exp3.db_info
....\..\exp3.eda.qmsg
....\..\exp3.fit.qmsg
....\..\exp3.hier_info
....\..\exp3.hif
....\..\exp3.idb.cdb
....\..\exp3.lpc.html
....\..\exp3.lpc.rdb
....\..\exp3.lpc.txt
....\..\exp3.map.bpm
....\..\exp3.map.cdb
....\..\exp3.map.hdb
....\..\exp3.map.kpt
....\..\exp3.map.logdb
....\..\exp3.map.qmsg
....\..\exp3.map_bb.cdb
....\..\exp3.map_bb.hdb
....\..\exp3.map_bb.logdb
....\..\exp3.pre_map.cdb
....\..\exp3.pre_map.hdb
....\..\exp3.rtlv.hdb
....\..\exp3.rtlv_sg.cdb
....\..\exp3.rtlv_sg_swap.cdb
....\..\exp3.sgdiff.cdb
....\..\exp3.sgdiff.hdb
....\..\exp3.sld_design_entry.sci
....\..\exp3.sld_design_entry_dsc.sci
....\..\exp3.smart_action.txt
....\..\exp3.smp_dump.txt
....\..\exp3.sta.qmsg
....\..\exp3.sta.rdb
....\..\exp3.sta_cmp.6_slow.tdb
....\..\exp3.syn_hier_info
....\..\exp3.tis_db_list.ddb
....\..\exp3.tmw_info
....\..\logic_util_heursitic.dat
....\..\prev_cmp_exp3.qmsg
....\exp3.asm.rpt
....\exp3.done
....\exp3.eda.rpt
....\exp3.fit.rpt
....\exp3.fit.smsg
....\exp3.fit.summary
....\exp3.flow.rpt
....\exp3.map.rpt
....\exp3.map.summary
....\exp3.pin
....\exp3.pof
....\exp3.qpf
....\exp3.qsf
....\exp3.sof
....\exp3.sta.rpt
....\exp3.sta.summary
....\exp3_nativelink_simulation.rpt
....\incremental_db
....\..............\README
....\..............\compiled_partitions
....\..............\...................\exp3.db_info
....\..............\...................\exp3.root_partition.cmp.cdb
....\..............\...................\exp3.root_partition.cmp.dfp
....\..............\...................\exp3.root_partition.cmp.hdb
....\..............\...................\exp3.root_partition.cmp.kpt
....\..............\...................\exp3.root_partition.cmp.logdb
....\..............\...................\exp3.root_partition.cmp.rcfdb
....\..............\...................\exp3.root_partition.map.cdb
....\..............\...................\exp3.root_partition.map.dpi
....\..............\...................\exp3.root_partition.map.hbdb.cdb
....\..............\...................\exp3.root_partition.map.hbdb.hb_info
....\..............\...................\exp3.root_partition.map.hbdb.hdb
....\..............\...................\exp3.root_partition.map.hbdb.sig
....\..............\...................\exp3.root_partition.map.hdb
....\..............\...................\exp3.root_partition.map.kpt
....\simulation
....\..........\modelsim
....\..........\........\controller.vt
....\..........\........\controller_ont_hot.vt
....\..........\........\exp3.sft
....\..........\........\exp3.vo
....\..........\........\exp3_fast.vo
....\..........\........\exp3_modelsim.xrf
....\..........\........\exp3_run_msim_rtl_verilog.do
....\..........\........\exp3_run_msim_rtl_verilog.do.bak
....\..........\........\exp3_run_msim_rtl_verilog.do.bak1
....\..........\........\exp3_run_msim_rtl_verilog.do.bak10
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