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interpolation

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-04-29
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vivado project file for down scaling of image by scale factor 2
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interpolation\inputHex.coe
.............\..terpolation.cache\wt\java_command_handlers.wdf
.............\...................\..\project.wpc
.............\...................\..\synthesis.wdf
.............\...................\..\synthesis_details.wdf
.............\...................\..\webtalk_pa.xml
.............\...................\..\xsim.wdf
.............\..............hw\interpolation.lpr
.............\................\webtalk\.xsim_webtallk.info
.............\................\.......\labtool_webtalk.log
.............\................\.......\usage_statistics_ext_labtool.html
.............\................\.......\usage_statistics_ext_labtool.xml
.............\..............ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.veo
.............\...........................\..\.............\blk_mem_gen_0.vho
.............\...........................\..\.............\blk_mem_gen_0_stub.v
.............\...........................\..\.............\blk_mem_gen_0_stub.vhdl
.............\...........................\..static\blk_mem_gen_v8_3_2\simulation\blk_mem_gen_v8_3.v
.............\...........................\mem_init_files\blk_mem_gen_0.mif
.............\...........................\..............\inputHex.coe
.............\...........................\..............\summary.log
.............\...........................\README.txt
.............\...........................\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.mif
.............\...........................\...........\.............\.........\blk_mem_gen_0.sh
.............\...........................\...........\.............\.........\blk_mem_gen_0.udo
.............\...........................\...........\.............\.........\compile.do
.............\...........................\...........\.............\.........\file_info.txt
.............\...........................\...........\.............\.........\glbl.v
.............\...........................\...........\.............\.........\inputHex.coe
.............\...........................\...........\.............\.........\README.txt
.............\...........................\...........\.............\.........\simulate.do
.............\...........................\...........\.............\.........\summary.log
.............\...........................\...........\.............\.........\wave.do
.............\...........................\...........\.............\ies\blk_mem_gen_0.mif
.............\...........................\...........\.............\...\blk_mem_gen_0.sh
.............\...........................\...........\.............\...\file_info.txt
.............\...........................\...........\.............\...\glbl.v
.............\...........................\...........\.............\...\inputHex.coe
.............\...........................\...........\.............\...\README.txt
.............\...........................\...........\.............\...\run.f
.............\...........................\...........\.............\...\summary.log
.............\...........................\...........\.............\modelsim\blk_mem_gen_0.mif
.............\...........................\...........\.............\........\blk_mem_gen_0.sh
.............\...........................\...........\.............\........\blk_mem_gen_0.udo
.............\...........................\...........\.............\........\compile.do
.............\...........................\...........\.............\........\file_info.txt
.............\...........................\...........\.............\........\glbl.v
.............\...........................\...........\.............\........\inputHex.coe
.............\...........................\...........\.............\........\README.txt
.............\...........................\...........\.............\........\simulate.do
.............\...........................\...........\.............\........\summary.log
.............\...........................\...........\.............\........\wave.do
.............\...........................\...........\.............\questa\blk_mem_gen_0
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