8 bit shift register with synchronous parallel preset function. The principle of work when the rising edge of CLK when the process is started, if the preset enable LOAD to a high level, the 8 bit binary number will be in the input port of the parallel shift register, serial output shift as the initial value if LOAD is low, then the statement is d: Reg8 (6 downto) < reg8 (7 downto 1)

shft.acf
shft.fit
shft.hif
shft.jam
shft.jbc
shft.mmf
shft.ndb
shft.pin
shft.pof
shft.rpt
shft.scf
shft.snf
SHFT.sym
shft.vhd

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