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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-05-16
  • Size : 43kb
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  • Author :王***
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Introduction - If you have any usage issues, please Google them yourself
DDS is implemented by look-up table, with MATLAB sampling
Packet file list
(Preview for download)


DDS频率合成电路设计\DC\area.txt
...................\..\check_design.txt
...................\..\check_timing.txt
...................\..\clock.txt
...................\..\con_violators.txt
...................\..\dc.txt
...................\..\timing_hold.txt
...................\..\timing_setup.txt
...................\..\top_net_fanout.txt
...................\..\wlm.txt
...................\PT\clock.txt
...................\..\con_violators.txt
...................\..\pt.txt
...................\..\timing_o.txt
...................\..\timing_rd.txt
...................\..\timing_setup.txt
...................\..\top.txt
...................\..\wlm.txt
...................\top.sv.txt
...................\设计代码\cpu.v
...................\........\dds.v
...................\........\rom.v
...................\........\test_dds.v
...................\........\top.v
...................\DC
...................\PT
...................\设计代码
DDS频率合成电路设计
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