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UART1
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VHDL-FPGA-Verilog
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Update : 2017-07-06
Size : 214kb
Downloaded :0次
Author :
奥卡姆***
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Introduction - If you have any usage issues, please Google them yourself
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Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication
Packet file list
(Preview for download)
UART1\UART.cache\wt\gui_resources.wdf
UART1\UART.cache\wt\java_command_handlers.wdf
UART1\UART.cache\wt\project.wpc
UART1\UART.cache\wt\synthesis.wdf
UART1\UART.cache\wt\synthesis_details.wdf
UART1\UART.cache\wt\webtalk_pa.xml
UART1\UART.cache\wt\xsim.wdf
UART1\UART.hw\UART.lpr
UART1\UART.ip_user_files\README.txt
UART1\UART.runs\.jobs\vrs_config_1.xml
UART1\UART.runs\.jobs\vrs_config_2.xml
UART1\UART.runs\synth_1\.vivado.begin.rst
UART1\UART.runs\synth_1\.vivado.end.rst
UART1\UART.runs\synth_1\.Vivado_Synthesis.queue.rst
UART1\UART.runs\synth_1\gen_run.xml
UART1\UART.runs\synth_1\htr.txt
UART1\UART.runs\synth_1\ISEWrap.js
UART1\UART.runs\synth_1\ISEWrap.sh
UART1\UART.runs\synth_1\project.wdf
UART1\UART.runs\synth_1\rundef.js
UART1\UART.runs\synth_1\runme.bat
UART1\UART.runs\synth_1\runme.log
UART1\UART.runs\synth_1\runme.sh
UART1\UART.runs\synth_1\uart_top.dcp
UART1\UART.runs\synth_1\uart_top.tcl
UART1\UART.runs\synth_1\uart_top.vds
UART1\UART.runs\synth_1\uart_top_utilization_synth.pb
UART1\UART.runs\synth_1\uart_top_utilization_synth.rpt
UART1\UART.runs\synth_1\vivado.jou
UART1\UART.runs\synth_1\vivado.pb
UART1\UART.sim\sim_1\behav\compile.bat
UART1\UART.sim\sim_1\behav\compile.log
UART1\UART.sim\sim_1\behav\elaborate.bat
UART1\UART.sim\sim_1\behav\elaborate.log
UART1\UART.sim\sim_1\behav\glbl.v
UART1\UART.sim\sim_1\behav\simulate.bat
UART1\UART.sim\sim_1\behav\simulate.log
UART1\UART.sim\sim_1\behav\uart_top.tcl
UART1\UART.sim\sim_1\behav\uart_top_behav.wdb
UART1\UART.sim\sim_1\behav\uart_top_vlog.prj
UART1\UART.sim\sim_1\behav\webtalk.jou
UART1\UART.sim\sim_1\behav\webtalk.log
UART1\UART.sim\sim_1\behav\webtalk_14244.backup.jou
UART1\UART.sim\sim_1\behav\webtalk_14244.backup.log
UART1\UART.sim\sim_1\behav\xelab.pb
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\Compile_Options.txt
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\TempBreakPointFile.txt
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\webtalk\.xsim_webtallk.info
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\webtalk\usage_statistics_ext_xsim.html
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\webtalk\usage_statistics_ext_xsim.xml
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.dbg
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.mem
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.reloc
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.rtti
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.svtype
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.type
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsim.xdbg
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsimcrash.log
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsimk.exe
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsimkernel.log
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\xsimSettings.ini
UART1\UART.sim\sim_1\behav\xsim.dir\xil_defaultlib\glbl.sdb
UART1\UART.sim\sim_1\behav\xsim.dir\xil_defaultlib\uart_rx_path.sdb
UART1\UART.sim\sim_1\behav\xsim.dir\xil_defaultlib\uart_top.sdb
UART1\UART.sim\sim_1\behav\xsim.dir\xil_defaultlib\uart_tx_path.sdb
UART1\UART.sim\sim_1\behav\xsim.dir\xil_defaultlib\xil_defaultlib.rlx
UART1\UART.sim\sim_1\behav\xsim.dir\xsim.svtype
UART1\UART.sim\sim_1\behav\xsim.ini
UART1\UART.sim\sim_1\behav\xvlog.log
UART1\UART.sim\sim_1\behav\xvlog.pb
UART1\UART.srcs\constrs_1\new\uart_top.xdc
UART1\UART.srcs\sources_1\bd\design_1\design_1.bd
UART1\UART.srcs\sources_1\bd\design_1\design_1.bxml
UART1\UART.srcs\sources_1\bd\design_1\ip\design_1_processing_system7_0_0\design_1_processing_system7_0_0.xci
UART1\UART.srcs\sources_1\bd\design_1\ip\design_1_processing_system7_0_0\design_1_processing_system7_0_0.xml
UART1\UART.srcs\sources_1\bd\design_1\ip\design_1_processing_system7_0_0_1\design_1_processing_system7_0_0.xci
UART1\UART.srcs\sources_1\bd\design_1\ip\design_1_processing_system7_0_0_1\design_1_processing_system7_0_0.xml
UART1\UART.srcs\sources_1\new\1.v
UART1\UART.srcs\sources_1\new\uart_rx_path.v
UART1\UART.srcs\sources_1\new\uart_top.v
UART1\UART.srcs\sources_1\new\uart_tx_pat.v
UART1\UART.xpr
UART1\vivado.jou
UART1\vivado.log
UART1\vivado_10492.backup.jou
UART1\vivado_10492.backup.log
UART1\vivado_10732.backup.jou
UART1\vivado_10732.backup.log
UART1\vivado_3332.backup.jou
UART1\vivado_3332.backup.log
UART1\vivado_5080.backup.jou
UART1\vivado_5080.backup.log
UART1\UART.sim\sim_1\behav\.Xil\Webtalk-12160-DESKTOP-573HOUM\webtalk
UART1\UART.sim\sim_1\behav\.Xil\Webtalk-14244-DESKTOP-573HOUM\webtalk
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav\webtalk
UART1\UART.srcs\sources_1\bd\design_1\ip\design_1_processing_system7_0_0
UART1\UART.srcs\sources_1\bd\design_1\ip\design_1_processing_system7_0_0_1
UART1\UART.sim\sim_1\behav\.Xil\Webtalk-12160-DESKTOP-573HOUM
UART1\UART.sim\sim_1\behav\.Xil\Webtalk-14244-DESKTOP-573HOUM
UART1\UART.sim\sim_1\behav\xsim.dir\uart_top_behav
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