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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-07-06
  • Size : 6kb
  • Downloaded :0次
  • Author :su***
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Introduction - If you have any usage issues, please Google them yourself
Use this code to practice zynq library
Packet file list
(Preview for download)
Lab3
Lab3\uvc
Lab3\uvc\fifo_agent.sv
Lab3\uvc\fifo_env.sv
Lab3\uvc\fifo_driver.sv
Lab3\README_FIRST.txt
Lab3\top
Lab3\top\fifo_top.sv
Lab3\sim
Lab3\sim\run
Lab3\test
Lab3\test\fifo_test.sv
Lab3\package
Lab3\package\fifo_pkg.sv
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