code for Master side

spi-master
spi-master\bench
spi-master\bench\verilog
spi-master\bench\verilog\spi_slave_model.v
spi-master\bench\verilog\tb_spi_top.v
spi-master\bench\verilog\wb_master_model.v
spi-master\doc
spi-master\doc\spi.pdf
spi-master\doc\src
spi-master\doc\src\spi.doc
spi-master\rtl
spi-master\rtl\verilog
spi-master\rtl\verilog\spi_clgen.v
spi-master\rtl\verilog\spi_defines.v
spi-master\rtl\verilog\spi_shift.v
spi-master\rtl\verilog\spi_top.v
spi-master\rtl\verilog\timescale.v
spi-master\sim
spi-master\sim\rtl_sim
spi-master\sim\rtl_sim\run
spi-master\sim\rtl_sim\run\rtl.fl
spi-master\sim\rtl_sim\run\run_sim
spi-master\sim\rtl_sim\run\sim.fl

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