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AD9512_test

  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-07-06
  • Size : 464kb
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  • Author :木*****
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Introduction - If you have any usage issues, please Google them yourself
Clock chip AD9512 debugging, achieve use successfully
Packet file list
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AD9512_test
AD9512_test\AD9512_test.gise
AD9512_test\AD9512_test.xise
AD9512_test\AD9512_test1.bld
AD9512_test\AD9512_test1.cmd_log
AD9512_test\AD9512_test1.lso
AD9512_test\AD9512_test1.ncd
AD9512_test\AD9512_test1.ngc
AD9512_test\AD9512_test1.ngd
AD9512_test\AD9512_test1.ngr
AD9512_test\AD9512_test1.pad
AD9512_test\AD9512_test1.par
AD9512_test\AD9512_test1.pcf
AD9512_test\AD9512_test1.prj
AD9512_test\AD9512_test1.ptwx
AD9512_test\AD9512_test1.stx
AD9512_test\AD9512_test1.syr
AD9512_test\AD9512_test1.twr
AD9512_test\AD9512_test1.twx
AD9512_test\AD9512_test1.unroutes
AD9512_test\AD9512_test1.ut
AD9512_test\AD9512_test1.v
AD9512_test\AD9512_test1.xpi
AD9512_test\AD9512_test1.xst
AD9512_test\AD9512_test1_bitgen.xwbt
AD9512_test\AD9512_test1_envsettings.html
AD9512_test\AD9512_test1_guide.ncd
AD9512_test\AD9512_test1_map.map
AD9512_test\AD9512_test1_map.mrp
AD9512_test\AD9512_test1_map.ncd
AD9512_test\AD9512_test1_map.ngm
AD9512_test\AD9512_test1_map.xrpt
AD9512_test\AD9512_test1_ngdbuild.xrpt
AD9512_test\AD9512_test1_pad.csv
AD9512_test\AD9512_test1_pad.txt
AD9512_test\AD9512_test1_par.xrpt
AD9512_test\AD9512_test1_summary.html
AD9512_test\AD9512_test1_summary.xml
AD9512_test\AD9512_test1_usage.xml
AD9512_test\AD9512_test1_xst.xrpt
AD9512_test\CLK_10M.tfi
AD9512_test\CLK_10M.v
AD9512_test\CLK_10M_arwz.ucf
AD9512_test\_ngo
AD9512_test\_ngo\netlist.lst
AD9512_test\_xmsgs
AD9512_test\_xmsgs\bitgen.xmsgs
AD9512_test\_xmsgs\map.xmsgs
AD9512_test\_xmsgs\ngdbuild.xmsgs
AD9512_test\_xmsgs\par.xmsgs
AD9512_test\_xmsgs\pn_parser.xmsgs
AD9512_test\_xmsgs\trce.xmsgs
AD9512_test\_xmsgs\xst.xmsgs
AD9512_test\ad9512_test1.bgn
AD9512_test\ad9512_test1.bit
AD9512_test\ad9512_test1.drc
AD9512_test\ipcore_dir
AD9512_test\ipcore_dir\CLK_10M.v
AD9512_test\ipcore_dir\CLK_10M.xaw
AD9512_test\ipcore_dir\CLK_10M_arwz.ucf
AD9512_test\ipcore_dir\CLK_10M_flist.txt
AD9512_test\ipcore_dir\_xmsgs
AD9512_test\ipcore_dir\_xmsgs\cg.xmsgs
AD9512_test\ipcore_dir\_xmsgs\pn_parser.xmsgs
AD9512_test\ipcore_dir\blk_mem_gen_ds512.pdf
AD9512_test\ipcore_dir\blk_mem_gen_v6_3
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\example_design
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\example_design\blk_mem_gen_v6_3_top.ucf
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\example_design\blk_mem_gen_v6_3_top.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\example_design\blk_mem_gen_v6_3_top.xdc
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\example_design\bmg_wrapper.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\implement.bat
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\implement.sh
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\planAhead_rdn.bat
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\planAhead_rdn.sh
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\planAhead_rdn.tcl
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\xst.prj
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\implement\xst.scr
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\addr_gen.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_stim_gen.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_tb_pkg.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_tb_synth.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\bmg_tb_top.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\isim_tcl_cmds.tcl
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\simulate_isim.bat
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\simulate_mti.do
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\simulate_ncsim.sh
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\wave_mti.do
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\functional\wave_ncsim.sv
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\random.vhd
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\isim_tcl_cmds.tcl
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\simulate_isim.bat
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\simulate_mti.do
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\simulate_ncsim.sh
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\wave_mti.do
AD9512_test\ipcore_dir\blk_mem_gen_v6_3\simulation\timing\wave_ncsim.sv
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