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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-07-06
  • Size : 252kb
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  • Author :凌风***
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Introduction - If you have any usage issues, please Google them yourself
Carry addition, to achieve the addition function of two numbers, can be extended to the number of add
Packet file list
(Preview for download)
adder
adder\adder.asm.rpt
adder\adder.done
adder\adder.eda.rpt
adder\adder.fit.rpt
adder\adder.fit.smsg
adder\adder.fit.summary
adder\adder.flow.rpt
adder\adder.map.rpt
adder\adder.map.summary
adder\adder.pin
adder\adder.pof
adder\adder.qpf
adder\adder.qsf
adder\adder.sof
adder\adder.tan.rpt
adder\adder.tan.summary
adder\adder.v
adder\adder_nativelink_simulation.rpt
adder\db
adder\db\adder.amm.cdb
adder\db\adder.asm.qmsg
adder\db\adder.asm.rdb
adder\db\adder.cbx.xml
adder\db\adder.cmp.cbp
adder\db\adder.cmp.kpt
adder\db\adder.cmp.rdb
adder\db\adder.cmp0.ddb
adder\db\adder.cmp2.ddb
adder\db\adder.cmp_merge.kpt
adder\db\adder.db_info
adder\db\adder.eda.qmsg
adder\db\adder.fit.qmsg
adder\db\adder.hier_info
adder\db\adder.hif
adder\db\adder.idb.cdb
adder\db\adder.lpc.html
adder\db\adder.lpc.rdb
adder\db\adder.lpc.txt
adder\db\adder.map.bpm
adder\db\adder.map.cbp
adder\db\adder.map.cdb
adder\db\adder.map.hdb
adder\db\adder.map.kpt
adder\db\adder.map.logdb
adder\db\adder.map.qmsg
adder\db\adder.map_bb.cdb
adder\db\adder.map_bb.hdb
adder\db\adder.map_bb.logdb
adder\db\adder.pre_map.cdb
adder\db\adder.pre_map.hdb
adder\db\adder.rtlv.hdb
adder\db\adder.rtlv_sg.cdb
adder\db\adder.rtlv_sg_swap.cdb
adder\db\adder.sgdiff.cdb
adder\db\adder.sgdiff.hdb
adder\db\adder.sld_design_entry.sci
adder\db\adder.sld_design_entry_dsc.sci
adder\db\adder.smart_action.txt
adder\db\adder.syn_hier_info
adder\db\adder.tan.qmsg
adder\db\adder.tis_db_list.ddb
adder\db\adder.tmw_info
adder\db\logic_util_heursitic.dat
adder\db\prev_cmp_adder.qmsg
adder\incremental_db
adder\incremental_db\README
adder\incremental_db\compiled_partitions
adder\incremental_db\compiled_partitions\adder.db_info
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.cdb
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.dfp
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.hdb
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.kpt
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.logdb
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.rcfdb
adder\incremental_db\compiled_partitions\adder.root_partition.cmp.re.rcfdb
adder\incremental_db\compiled_partitions\adder.root_partition.map.cdb
adder\incremental_db\compiled_partitions\adder.root_partition.map.dpi
adder\incremental_db\compiled_partitions\adder.root_partition.map.hdb
adder\incremental_db\compiled_partitions\adder.root_partition.map.kpt
adder\simulation
adder\simulation\modelsim
adder\simulation\modelsim\adder.sft
adder\simulation\modelsim\adder.vo
adder\simulation\modelsim\adder.vt
adder\simulation\modelsim\adder_modelsim.xrf
adder\simulation\modelsim\adder_run_msim_rtl_verilog.do
adder\simulation\modelsim\adder_run_msim_rtl_verilog.do.bak1
adder\simulation\modelsim\adder_run_msim_rtl_verilog.do.bak2
adder\simulation\modelsim\adder_run_msim_rtl_verilog.do.bak3
adder\simulation\modelsim\adder_run_msim_rtl_verilog.do.bak4
adder\simulation\modelsim\adder_v.sdo
adder\simulation\modelsim\msim_transcript
adder\simulation\modelsim\rtl_work
adder\simulation\modelsim\rtl_work\_info
adder\simulation\modelsim\rtl_work\_temp
adder\simulation\modelsim\rtl_work\_vmake
adder\simulation\modelsim\rtl_work\adder
adder\simulation\modelsim\rtl_work\adder\_primary.dat
adder\simulation\modelsim\rtl_work\adder\_primary.dbs
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