Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row, and then read out by column; deinterleaving process is the first data written by the column, then read by line. It is characterized by a simple structure, but the data delay time is long, and the required memory is relatively large.

1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\decode_addr
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\decode_addr\decode_addr.png
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\decode_addr\decode_addr.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\decode_addr\test.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\encode_addr
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1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\encode_addr\encode_addr.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\encode_addr\test.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver\interleaver.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver\interleaver_1.png
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1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver\interleaver_tb.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\decode_addr
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\decode_addr\verilog.asm
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\decode_addr\verilog.rw
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\decode_addr\_primary.dat
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\decode_addr\_primary.dbs
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\decode_addr\_primary.vhd
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\encode_addr
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\encode_addr\verilog.asm
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\encode_addr\verilog.rw
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\encode_addr\_primary.dat
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\encode_addr\_primary.dbs
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\encode_addr\_primary.vhd
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver\verilog.asm
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver\verilog.rw
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver\_primary.dat
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver\_primary.dbs
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver\_primary.vhd
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver_tb
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver_tb\verilog.asm
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1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver_tb\_primary.dat
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver_tb\_primary.dbs
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\interleaver_tb\_primary.vhd
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\ram_2048
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\ram_2048\verilog.asm
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1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\ram_2048\_primary.dat
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\ram_2048\_primary.dbs
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\ram_2048\_primary.vhd
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\seq_gen
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\seq_gen\verilog.asm
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\seq_gen\verilog.rw
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\seq_gen\_primary.dat
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\seq_gen\_primary.dbs
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\seq_gen\_primary.vhd
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\_info
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\_temp
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\interleaver_testbench\_vmake
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\ram_2048
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\ram_2048\ram_2048.png
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\ram_2048\ram_2048.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\readme.txt
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\seq_gen
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1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\seq_gen\seq_gen.v
1.鍗风Н浜ょ粐鍣ㄨВ浜ょ粐鍣ㄤ唬鐮?testbench\seq_gen\test.v
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