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  • Category : VHDL-FPGA-Verilog
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  • Update : 2017-07-07
  • Size : 286kb
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  • Author :leopard*******
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Introduction - If you have any usage issues, please Google them yourself
AD9777 chip design based on FPGA platform code
Packet file list
(Preview for download)
AD9777
AD9777\ad9777_spi_interface
AD9777\ad9777_spi_interface.v
AD9777\ad9777_spi_interface.v.bak
AD9777\ad9777_spi_interface\verilog.psm
AD9777\ad9777_spi_interface\_primary.dat
AD9777\ad9777_spi_interface\_primary.vhd
AD9777\config_dac
AD9777\config_dac.asm.rpt
AD9777\config_dac.done
AD9777\config_dac.eda.rpt
AD9777\config_dac.fit.rpt
AD9777\config_dac.fit.smsg
AD9777\config_dac.fit.summary
AD9777\config_dac.flow.rpt
AD9777\config_dac.map.rpt
AD9777\config_dac.map.smsg
AD9777\config_dac.map.summary
AD9777\config_dac.pin
AD9777\config_dac.pof
AD9777\config_dac.qpf
AD9777\config_dac.qsf
AD9777\config_dac.qws
AD9777\config_dac.sof
AD9777\config_dac.tan.rpt
AD9777\config_dac.tan.summary
AD9777\config_dac.v
AD9777\config_dac.v.bak
AD9777\config_dac\verilog.psm
AD9777\config_dac\_primary.dat
AD9777\config_dac\_primary.vhd
AD9777\db
AD9777\db\config_dac.asm.qmsg
AD9777\db\config_dac.cbx.xml
AD9777\db\config_dac.cmp.ecobp
AD9777\db\config_dac.cmp.rdb
AD9777\db\config_dac.cmp0.ddb
AD9777\db\config_dac.cmp_bb.cdb
AD9777\db\config_dac.cmp_bb.hdb
AD9777\db\config_dac.cmp_bb.logdb
AD9777\db\config_dac.cmp_bb.rcf
AD9777\db\config_dac.dbp
AD9777\db\config_dac.db_info
AD9777\db\config_dac.eco.cdb
AD9777\db\config_dac.eda.qmsg
AD9777\db\config_dac.fit.qmsg
AD9777\db\config_dac.hier_info
AD9777\db\config_dac.hif
AD9777\db\config_dac.map.ecobp
AD9777\db\config_dac.map.qmsg
AD9777\db\config_dac.map_bb.hdb
AD9777\db\config_dac.map_bb.logdb
AD9777\db\config_dac.pre_map.cdb
AD9777\db\config_dac.pre_map.hdb
AD9777\db\config_dac.psp
AD9777\db\config_dac.pss
AD9777\db\config_dac.rtlv.hdb
AD9777\db\config_dac.rtlv_sg.cdb
AD9777\db\config_dac.rtlv_sg_swap.cdb
AD9777\db\config_dac.sgdiff.cdb
AD9777\db\config_dac.sgdiff.hdb
AD9777\db\config_dac.sld_design_entry.sci
AD9777\db\config_dac.sld_design_entry_dsc.sci
AD9777\db\config_dac.smp_dump.txt
AD9777\db\config_dac.syn_hier_info
AD9777\db\config_dac.tan.qmsg
AD9777\db\prev_cmp_config_dac.asm.qmsg
AD9777\db\prev_cmp_config_dac.eda.qmsg
AD9777\db\prev_cmp_config_dac.fit.qmsg
AD9777\db\prev_cmp_config_dac.map.qmsg
AD9777\db\prev_cmp_config_dac.tan.qmsg
AD9777\prev_cmp_config_dac.qmsg
AD9777\simulation
AD9777\simulation\modelsim
AD9777\simulation\modelsim\config_dac.vo
AD9777\simulation\modelsim\config_dac_modelsim.xrf
AD9777\simulation\modelsim\config_dac_v.sdo
AD9777\test_config_dac
AD9777\test_config_dac.v
AD9777\test_config_dac.v.bak
AD9777\test_config_dac\verilog.psm
AD9777\test_config_dac\_primary.dat
AD9777\test_config_dac\_primary.vhd
AD9777\_info
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