Altera Edge Detection for FPGA

Extras_Edge_Detection\app_software
Extras_Edge_Detection\app_software\edge_detection.ncf
Extras_Edge_Detection\verilog
Extras_Edge_Detection\verilog\altera_up_av_config_auto_init.v
Extras_Edge_Detection\verilog\altera_up_av_config_auto_init_ob_adv7181.v
Extras_Edge_Detection\verilog\altera_up_av_config_auto_init_ob_audio.v
Extras_Edge_Detection\verilog\altera_up_av_config_auto_init_ob_de2_35.v
Extras_Edge_Detection\verilog\altera_up_av_config_serial_bus_controller.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\altera_up_avalon_audio_and_video_config_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\altera_up_avalon_audio_and_video_config_sw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL\inc
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL\inc\altera_up_avalon_audio_and_video_config.h
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL\inc\altera_up_avalon_audio_and_video_config_regs.h
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL\src
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL\src\altera_up_avalon_audio_and_video_config.c
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\HAL\src\component.mk
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_d5m.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_dc2.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_lcm.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ltm.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ob_adv7180.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ob_adv7181.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ob_audio.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ob_de2_115.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ob_de2_35.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_auto_init_ob_de2_70.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_av_config_serial_bus_controller.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_avalon_av_config.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\altera_up_slow_clock_generator.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\hdl\Copy of altera_up_avalon_av_config.v
Extras_Edge_Detection\verilog\altera_up_avalon_audio_and_video_config\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_clocks
Extras_Edge_Detection\verilog\altera_up_avalon_clocks\altera_up_avalon_clocks_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_clocks\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_clocks\hdl\altera_up_avalon_clocks.v
Extras_Edge_Detection\verilog\altera_up_avalon_clocks\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_sram
Extras_Edge_Detection\verilog\altera_up_avalon_sram\altera_up_avalon_sram_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_sram\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_sram\hdl\altera_up_avalon_sram.v
Extras_Edge_Detection\verilog\altera_up_avalon_sram\hdl\altera_up_avalon_ssram.v
Extras_Edge_Detection\verilog\altera_up_avalon_sram\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\altera_up_avalon_video_alpha_blender_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\hdl\altera_up_avalon_video_alpha_blender.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\hdl\altera_up_avalon_video_alpha_blender_normal.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\hdl\altera_up_avalon_video_alpha_blender_simple.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\hdl\altera_up_video_alpha_blender_normal.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\hdl\altera_up_video_alpha_blender_simple.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_alpha_blender\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\altera_up_avalon_video_bayer_resampler_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\hdl\altera_up_avalon_video_bayer_resampler.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\modelsim
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\modelsim\bayer_resampler_testbench.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\modelsim\tb.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\modelsim\w.do
Extras_Edge_Detection\verilog\altera_up_avalon_video_bayer_resampler\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\altera_up_avalon_video_character_buffer_with_dma_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\altera_up_avalon_video_character_buffer_with_dma_sw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL\inc
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL\inc\altera_up_avalon_video_character_buffer_with_dma.h
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL\inc\altera_up_avalon_video_character_buffer_with_dma_regs.h
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL\src
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL\src\altera_up_avalon_video_character_buffer_with_dma.c
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\HAL\src\component.mk
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\hdl\altera_up_avalon_video_character_buffer_with_dma.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\hdl\altera_up_video_128_character_rom.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\hdl\altera_up_video_char_mode_rom_128.mif
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\hdl\altera_up_video_fb_color_rom.mif
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\hdl\altera_up_video_fb_color_rom.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_character_buffer_with_dma\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_chroma_resampler
Extras_Edge_Detection\verilog\altera_up_avalon_video_chroma_resampler\altera_up_avalon_video_chroma_resampler_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_chroma_resampler\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_video_chroma_resampler\hdl\altera_up_avalon_video_chroma_resampler.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_chroma_resampler\up_ip_generator.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\altera_up_avalon_video_clipper_hw.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\hdl
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\hdl\altera_up_avalon_video_clipper.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\hdl\altera_up_video_clipper_add.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\hdl\altera_up_video_clipper_counters.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\hdl\altera_up_video_clipper_drop.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim\clipper_testbench.cr.mti
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim\clipper_testbench.mpf
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim\clipper_testbench.v
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim\tb.tcl
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim\vsim.wlf
Extras_Edge_Detection\verilog\altera_up_avalon_video_clipper\modelsim\w.do

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