FPGA using serial port, FIFO serial transceiver data

uartverilog
uartverilog\db
uartverilog\db\logic_util_heursitic.dat
uartverilog\db\my_uart_top.db_info
uartverilog\db\my_uart_top.eco.cdb
uartverilog\db\my_uart_top.sld_design_entry.sci
uartverilog\db\my_uart_top_global_asgn_op.abo
uartverilog\db\prev_cmp_my_uart_top.asm.qmsg
uartverilog\db\prev_cmp_my_uart_top.fit.qmsg
uartverilog\db\prev_cmp_my_uart_top.map.qmsg
uartverilog\db\prev_cmp_my_uart_top.qmsg
uartverilog\db\prev_cmp_my_uart_top.tan.qmsg
uartverilog\incremental_db
uartverilog\incremental_db\README
uartverilog\incremental_db\compiled_partitions
uartverilog\incremental_db\compiled_partitions\my_uart_top.db_info
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.cmp.cdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.cmp.dfp
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.cmp.hdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.cmp.kpt
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.cmp.logdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.cmp.rcfdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.cdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.dpi
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.hbdb.cdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.hbdb.hb_info
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.hbdb.hdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.hbdb.sig
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.hdb
uartverilog\incremental_db\compiled_partitions\my_uart_top.root_partition.map.kpt
uartverilog\my_uart_rx.v
uartverilog\my_uart_rx.v.bak
uartverilog\my_uart_top.asm.rpt
uartverilog\my_uart_top.cdf
uartverilog\my_uart_top.done
uartverilog\my_uart_top.fit.rpt
uartverilog\my_uart_top.fit.smsg
uartverilog\my_uart_top.fit.summary
uartverilog\my_uart_top.flow.rpt
uartverilog\my_uart_top.jpg
uartverilog\my_uart_top.map.rpt
uartverilog\my_uart_top.map.smsg
uartverilog\my_uart_top.map.summary
uartverilog\my_uart_top.pin
uartverilog\my_uart_top.pof
uartverilog\my_uart_top.qpf
uartverilog\my_uart_top.qsf
uartverilog\my_uart_top.qws
uartverilog\my_uart_top.sof
uartverilog\my_uart_top.sta.rpt
uartverilog\my_uart_top.sta.summary
uartverilog\my_uart_top.tan.rpt
uartverilog\my_uart_top.tan.summary
uartverilog\my_uart_top.v
uartverilog\my_uart_top.v.bak
uartverilog\my_uart_top_assignment_defaults.qdf
uartverilog\my_uart_tx.v
uartverilog\my_uart_tx.v.bak
uartverilog\output_file.jic
uartverilog\output_file.map
uartverilog\speed_select.v

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