A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.

8_1
8_1\db
8_1\db-eee.sim.tif
8_1\db\eee.db_info
8_1\db\eee.sim.cvwf
8_1\db\eee_global_asgn_op.abo
8_1\db\prev_cmp_eee.map.qmsg
8_1\db\prev_cmp_eee.qmsg
8_1\db\prev_cmp_eee.sim.qmsg
8_1\db\wed.wsf
8_1\eee.asm.rpt
8_1\eee.done
8_1\eee.fit.rpt
8_1\eee.fit.summary
8_1\eee.flow.rpt
8_1\eee.map.rpt
8_1\eee.map.summary
8_1\eee.pin
8_1\eee.pof
8_1\eee.qpf
8_1\eee.qsf
8_1\eee.sim.rpt
8_1\eee.sof
8_1\eee.tan.rpt
8_1\eee.tan.summary
8_1\eee.v
8_1\eee.v.bak
8_1\eee.vwf
8_1\incremental_db
8_1\incremental_db\compiled_partitions
8_1\incremental_db\compiled_partitions\eee.root_partition.cmp.atm
8_1\incremental_db\compiled_partitions\eee.root_partition.cmp.dfp
8_1\incremental_db\compiled_partitions\eee.root_partition.cmp.hdbx
8_1\incremental_db\compiled_partitions\eee.root_partition.cmp.kpt
8_1\incremental_db\compiled_partitions\eee.root_partition.cmp.logdb
8_1\incremental_db\compiled_partitions\eee.root_partition.cmp.rcf
8_1\incremental_db\compiled_partitions\eee.root_partition.map.atm
8_1\incremental_db\compiled_partitions\eee.root_partition.map.dpi
8_1\incremental_db\compiled_partitions\eee.root_partition.map.hdbx
8_1\incremental_db\compiled_partitions\eee.root_partition.map.kpt
8_1\incremental_db\README

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