Verilog implements a complete adder, including test files

add\add.done
add\add.eda.rpt
add\add.flow.rpt
add\add.map.rpt
add\add.map.summary
add\add.qpf
add\add.qsf
add\add.v
add\add.v.bak
add\add_nativelink_simulation.rpt
add\db\add.cbx.xml
add\db\add.cmp.hdb
add\db\add.cmp.rdb
add\db\add.db_info
add\db\add.eda.qmsg
add\db\add.hier_info
add\db\add.hif
add\db\add.lpc.html
add\db\add.lpc.rdb
add\db\add.lpc.txt
add\db\add.map.cdb
add\db\add.map.hdb
add\db\add.map.logdb
add\db\add.map.qmsg
add\db\add.pre_map.cdb
add\db\add.pre_map.hdb
add\db\add.rtlv.hdb
add\db\add.rtlv_sg.cdb
add\db\add.rtlv_sg_swap.cdb
add\db\add.sgdiff.cdb
add\db\add.sgdiff.hdb
add\db\add.sld_design_entry.sci
add\db\add.sld_design_entry_dsc.sci
add\db\add.smart_action.txt
add\db\add.syn_hier_info
add\db\add.tis_db_list.ddb
add\db\logic_util_heursitic.dat
add\db\prev_cmp_add.qmsg
add\incremental_db\compiled_partitions\add.db_info
add\incremental_db\compiled_partitions\add.root_partition.map.kpt
add\incremental_db\README
add\simulation\modelsim\add.vt
add\simulation\modelsim\add.vt.bak
add\simulation\modelsim\add_run_msim_rtl_verilog.do
add\simulation\modelsim\add_run_msim_rtl_verilog.do.bak
add\simulation\modelsim\msim_transcript
add\simulation\modelsim\rtl_work\@_opt\vopt22ajhw
add\simulation\modelsim\rtl_work\@_opt\vopt2deniv
add\simulation\modelsim\rtl_work\@_opt\vopt664ifv
add\simulation\modelsim\rtl_work\@_opt\vopt6z0g2w
add\simulation\modelsim\rtl_work\@_opt\vopt9rnczv
add\simulation\modelsim\rtl_work\@_opt\voptdyd9dv
add\simulation\modelsim\rtl_work\@_opt\voptg7030w
add\simulation\modelsim\rtl_work\@_opt\voptgvn6yk
add\simulation\modelsim\rtl_work\@_opt\voptkbc3yk
add\simulation\modelsim\rtl_work\@_opt\voptkqm00w
add\simulation\modelsim\rtl_work\@_opt\voptq7bxzv
add\simulation\modelsim\rtl_work\@_opt\voptqq7tmw
add\simulation\modelsim\rtl_work\@_opt\voptv7xqmw
add\simulation\modelsim\rtl_work\@_opt\voptvd1w7w
add\simulation\modelsim\rtl_work\@_opt\voptvq0szv
add\simulation\modelsim\rtl_work\@_opt\voptyqikmw
add\simulation\modelsim\rtl_work\@_opt\voptz8knkw
add\simulation\modelsim\rtl_work\@_opt\voptzjrsmv
add\simulation\modelsim\rtl_work\@_opt\_deps
add\simulation\modelsim\rtl_work\add\_primary.dat
add\simulation\modelsim\rtl_work\add\_primary.dbs
add\simulation\modelsim\rtl_work\add\_primary.vhd
add\simulation\modelsim\rtl_work\add_vlg_tst\_primary.dat
add\simulation\modelsim\rtl_work\add_vlg_tst\_primary.dbs
add\simulation\modelsim\rtl_work\add_vlg_tst\_primary.vhd
add\simulation\modelsim\rtl_work\_info
add\simulation\modelsim\rtl_work\_vmake
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_m_cntr\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_m_cntr\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_m_cntr\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_n_cntr\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_n_cntr\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_n_cntr\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_pll\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_pll\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_pll\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_scale_cntr\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_scale_cntr\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiiigl_scale_cntr\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiii_pll\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiii_pll\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_cycloneiii_pll\_primary.vhd
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_pll_reg\_primary.dat
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_pll_reg\_primary.dbs
add\simulation\modelsim\verilog_libs\altera_mf_ver\@m@f_pll_reg\_primary.vhd

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．