Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective

fadder_4v\db\fadder_4.ae.hdb
fadder_4v\db\fadder_4.cbx.xml
fadder_4v\db\fadder_4.cmp.rdb
fadder_4v\db\fadder_4.db_info
fadder_4v\db\fadder_4.eco.cdb
fadder_4v\db\fadder_4.eds_overflow
fadder_4v\db\fadder_4.fnsim.cdb
fadder_4v\db\fadder_4.fnsim.hdb
fadder_4v\db\fadder_4.fnsim.qmsg
fadder_4v\db\fadder_4.hier_info
fadder_4v\db\fadder_4.hif
fadder_4v\db\fadder_4.lpc.html
fadder_4v\db\fadder_4.lpc.rdb
fadder_4v\db\fadder_4.lpc.txt
fadder_4v\db\fadder_4.map.cdb
fadder_4v\db\fadder_4.map.hdb
fadder_4v\db\fadder_4.map.logdb
fadder_4v\db\fadder_4.map.qmsg
fadder_4v\db\fadder_4.pre_map.cdb
fadder_4v\db\fadder_4.pre_map.hdb
fadder_4v\db\fadder_4.rpp.qmsg
fadder_4v\db\fadder_4.rtlv.hdb
fadder_4v\db\fadder_4.rtlv_sg.cdb
fadder_4v\db\fadder_4.rtlv_sg_swap.cdb
fadder_4v\db\fadder_4.sgate.rvd
fadder_4v\db\fadder_4.sgate_sm.rvd
fadder_4v\db\fadder_4.sgdiff.cdb
fadder_4v\db\fadder_4.sgdiff.hdb
fadder_4v\db\fadder_4.sim.cvwf
fadder_4v\db\fadder_4.sim.hdb
fadder_4v\db\fadder_4.sim.qmsg
fadder_4v\db\fadder_4.sim.rdb
fadder_4v\db\fadder_4.simfam
fadder_4v\db\fadder_4.sld_design_entry.sci
fadder_4v\db\fadder_4.sld_design_entry_dsc.sci
fadder_4v\db\fadder_4.syn_hier_info
fadder_4v\db\fadder_4.tis_db_list.ddb
fadder_4v\db\fadder_4.tmw_info
fadder_4v\db\prev_cmp_fadder_4.map.qmsg
fadder_4v\db\prev_cmp_fadder_4.qmsg
fadder_4v\db\wed.wsf
fadder_4v\fadder_1.bsf
fadder_4v\fadder_4.bsf
fadder_4v\fadder_4.done
fadder_4v\fadder_4.dpf
fadder_4v\fadder_4.flow.rpt
fadder_4v\fadder_4.map.rpt
fadder_4v\fadder_4.map.summary
fadder_4v\fadder_4.qpf
fadder_4v\fadder_4.qsf
fadder_4v\fadder_4.qws
fadder_4v\fadder_4.sim.rpt
fadder_4v\fadder_4.v
fadder_4v\fadder_4.vwf
fadder_4v\incremental_db\compiled_partitions\fadder_4.root_partition.map.kpt
fadder_4v\incremental_db\README
fadder_4v\incremental_db\compiled_partitions
fadder_4v\db
fadder_4v\incremental_db
fadder_4v

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