Verilog io analog serial port, using io simulation UART serial communication, no hardware serial port

UART
UART\RX_receiver.v
UART\RX_receiver.v.bak
UART\TX_transmiter.v
UART\TX_transmiter.v.bak
UART\Waveform.vwf
UART\Waveform.vwf.temp
UART\Waveform1.vwf
UART\Waveform2.vwf
UART\Waveform3.vwf
UART\Waveform3.vwf.temp
UART\Waveform4.vwf
UART\clk_devider.v
UART\clk_devider.v.bak
UART\clk_devider_tx.v
UART\clk_devider_tx.v.bak
UART\controler.v
UART\controler.v.bak
UART\db
UART\db\.cmp.kpt
UART\db\logic_util_heursitic.dat
UART\db\prev_cmp_uart.qmsg
UART\db\uart.asm.qmsg
UART\db\uart.asm.rdb
UART\db\uart.cbx.xml
UART\db\uart.cmp.cdb
UART\db\uart.cmp.hdb
UART\db\uart.cmp.idb
UART\db\uart.cmp.logdb
UART\db\uart.cmp.rdb
UART\db\uart.cmp0.ddb
UART\db\uart.db_info
UART\db\uart.eda.qmsg
UART\db\uart.fit.qmsg
UART\db\uart.hier_info
UART\db\uart.hif
UART\db\uart.logic_util_heuristic.dat
UART\db\uart.lpc.html
UART\db\uart.lpc.rdb
UART\db\uart.lpc.txt
UART\db\uart.map.cdb
UART\db\uart.map.hdb
UART\db\uart.map.logdb
UART\db\uart.map.qmsg
UART\db\uart.map.rdb
UART\db\uart.npp.qmsg
UART\db\uart.pre_map.hdb
UART\db\uart.pti_db_list.ddb
UART\db\uart.root_partition.map.reg_db.cdb
UART\db\uart.routing.rdb
UART\db\uart.rtlv.hdb
UART\db\uart.rtlv_sg.cdb
UART\db\uart.rtlv_sg_swap.cdb
UART\db\uart.sgate.nvd
UART\db\uart.sgate_sm.nvd
UART\db\uart.sld_design_entry.sci
UART\db\uart.sld_design_entry_dsc.sci
UART\db\uart.smart_action.txt
UART\db\uart.sta.qmsg
UART\db\uart.sta.rdb
UART\db\uart.sta_cmp.5_slow.tdb
UART\db\uart.tis_db_list.ddb
UART\db\uart.tmw_info
UART\db\uart.vpr.ammdb
UART\incremental_db
UART\incremental_db\README
UART\incremental_db\compiled_partitions
UART\incremental_db\compiled_partitions\uart.db_info
UART\incremental_db\compiled_partitions\uart.root_partition.map.kpt
UART\modelsim.ini
UART\msim_transcript
UART\output_files
UART\output_files\uart.asm.rpt
UART\output_files\uart.done
UART\output_files\uart.eda.rpt
UART\output_files\uart.fit.rpt
UART\output_files\uart.fit.smsg
UART\output_files\uart.fit.summary
UART\output_files\uart.flow.rpt
UART\output_files\uart.jdi
UART\output_files\uart.map.rpt
UART\output_files\uart.map.smsg
UART\output_files\uart.map.summary
UART\output_files\uart.pin
UART\output_files\uart.pof
UART\output_files\uart.sta.rpt
UART\output_files\uart.sta.summary
UART\rtl_work
UART\rtl_work\_info
UART\rtl_work\_lib.qdb
UART\rtl_work\_lib1_0.qdb
UART\rtl_work\_lib1_0.qpg
UART\rtl_work\_lib1_0.qtl
UART\rtl_work\_vmake
UART\simulation
UART\simulation\modelsim
UART\simulation\modelsim\uart.sft
UART\simulation\modelsim\uart.vho
UART\simulation\modelsim\uart_modelsim.xrf
UART\simulation\modelsim\uart_vhd.sdo

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